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 DATA SHEET
MOS INTEGRATED CIRCUIT
PD17230,17231,17232,17233,17234,17235,17236
4-BIT SINGLE-CHIP MICROCONTROLLER FOR SMALL GENERAL-PURPOSE INFRARED REMOTE CONTROL TRANSMITTER
DESCRIPTION
PD17230, 17231, 17232, 17233, 17234, 17235, 17236 (hereafter called PD17236 subseries) are 4-bit singlechip microcontrollers for small general-purpose infrared remote control transmitters. It employs a 17K architecture of general-purpose register type devices for the CPU, and can directly execute operations between memories instead of the conventional method of executing operations through the accumulator. Moreover, all the instructions are 16-bit 1-word instructions which can be programmed efficiently. In addition, a one-time PROM model, PD17P236Note, to which data can be written only once, is also available. It is convenient either for evaluating the PD17236 subseries programs or small-scale production of application systems.
Note Under development
Detailed functions are described in the following manual. Be sure to read this manual when designing your system.
PD172xx Subseries User's Manual: U12795E
FEATURES
* Infrared remote controller carrier generator circuit (REM output) * 17K architecture: General-purpose register system * Program memory (ROM), Data memory (RAM)
PD17230
Program 4 K bytes 223 x 4 bits memory (ROM) (2048 x 16) Data memory (RAM)
PD17231
8 K bytes (4096 x 16)
PD17232
12 K bytes (6144 x 16)
PD17233
16 K bytes (8192 x 16)
PD17234
20 K bytes
PD17235
24 K bytes
PD17236
32 K bytes
(10240 x 16) (12288 x 16) (16384 x 16)
* 8-bit timer
: 1 channel
* Basic internal timer/Watchdog timer : 1 channel * Instruction execution time (can be changed in two steps) at fX = 4 MHz at fX = 8 MHz * External interrupt pin (INT) * I/O pins * Supply voltage : 4 s (high-speed mode)/8 s (ordinary mode) : 2 s (high-speed mode)/4 s (ordinary mode) :1 : 21 : VDD = 2.2 to 3.6 V (at fX = 8 MHz (high-speed mode)) VDD = 2.0 to 3.6 V (at fX = 4 MHz (high-speed mode))
* Low-voltage detector circuit (mask option) Unless otherwise specified, the PD17236 is treated as the representative model throughout this document.
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. U14360EJ1V0DS00 (1st edition) Date Published July 1999 N CP (K) Printed in Japan
(c)
1999
PD17230, 17231, 17232, 17233, 17234, 17235, 17236
APPLICATION
Preset remote controllers, toys, portable systems, etc.
ORDERING INFORMATION
Part Number Package 30-pin plastic shrink SOP (300 mil) 30-pin plastic shrink SOP (300 mil) 30-pin plastic shrink SOP (300 mil) 30-pin plastic shrink SOP (300 mil) 30-pin plastic shrink SOP (300 mil) 28-pin plastic SOP (375 mil) 30-pin plastic shrink SOP (300 mil) 28-pin plastic SOP (375 mil) 30-pin plastic shrink SOP (300 mil)
PD17230MC-xxx-5A4 PD17231MC-xxx-5A4 PD17232MC-xxx-5A4 PD17233MC-xxx-5A4 PD17234MC-xxx-5A4 PD17235GT-xxx PD17235MC-xxx-5A4 PD17236GT-xxx PD17236MC-xxx-5A4
Remark xxx indicates ROM code suffix.
DIFFERENCE BETWEEN PD17236 SUBSERIES AND PD17225 SUBSERIES
Item ROM capacity
PD17236 Subseries PD17230: PD17231: PD17232: PD17233: PD17234: PD17235: PD17236:
2048 x 16 bits 4096 x 16 bits 6144 x 16 bits 8192 x 16 bits 10240 x 16 bits 12288 x 16 bits 16384 x 16 bits
PD17225 Subseries PD17225: PD17226: PD17227: PD17228:
2048 4096 6144 8192 x x x x 16 16 16 16 bits bits bits bits
Port
P0B0-P0B3: I/O (bit I/O) P0C0-P0C3: I/O (group I/O) P0D0-P0D3: I/O (group I/O) P1A0: Input or output selectable by mask option RESET pin is internally pulled down by occurrence of the internal reset signals on the left, and reset takes place (usually, RESET pin is pulled up).
P0B0-P0B3: Input P0C0-P0C3: Output P0D0-P0D3: Output
Reset * Reset by watchdog timer * Reset by stack pointer * Low-voltage detection circuit (mask option) STOP mode release condition
Low level is output from WDOUT pin by occurrence of the internal reset signals on the left, and reset takes place if the WDOUT pin is externally connected to the RESET pin.
<1> When any of pins P0A0-P0A3 goes low <2> When P0B0-P0B3, P0C0-P0C3, and P0D0-P0D3 are used as input pins and any of them goes low <3> When the interrupt request (IRQ) of an interrupt for which IP flag is set is generated at rising or falling edge of INT pin Selected by mask option <1> If carrier generation clock (RfX) is fX/2: 7.8 kHz to 1 MHz <2> If carrier generation clock (RfX) is fX: 15.6 kHz to 2 MHz P1A0 pin
When any of P0A0-P0A3 or P0B0-P0B3 goes low
Carrier frequency (fX = 4 MHz)
7.8 kHz to 1 MHz
Pin 14
WDOUT pin
2
Data Sheet U14360EJ1V0DS00
PD17230, 17231, 17232, 17233, 17234, 17235, 17236
PIN CONFIGURATION (TOP VIEW)
* 28-pin plastic SOP (375 mil)
PD17235GT-xxx, 17236GT-xxx
P0D 2 P0D 3 INT P0E 0 P0E 1 P0E 2 P0E 3 REM V DD X OUT X IN GND RESET P1A0
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
P0D 1 P0D 0 P0C 3 P0C 2 P0C 1 P0C 0 P0B 3 P0B 2 P0B 1 P0B 0 P0A 3 P0A 2 P0A 1 P0A 0
Data Sheet U14360EJ1V0DS00
3
PD17230, 17231, 17232, 17233, 17234, 17235, 17236
* 30-pin plastic shrink SOP (300 mil)
PD17230MC-xxx-5A4, PD17231MC-xxx-5A4, PD17232MC-xxx-5A4, PD17233MC-xxx-5A4, PD17234MC-xxx-5A4, PD17235MC-xxx-5A4, PD17236MC-xxx-5A4
P0D2 P0D3 INT P0E0 P0E1 P0E2 P0E3 REM VDD XOUT XIN GND RESET P1A0 IC1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IC2 P0D1 P0D0 P0C3 P0C2 P0C1 P0C0 P0B3 P0B2 P0B1 P0B0 P0A3 P0A2 P0A1 P0A0
GND IC1, IC2 INT
: Ground : Internally connected : External interrupt request signal input
P0A0-P0A3 : Input port (CMOS input) P0B0-P0B3 : Input/output port (CMOS input/N-ch open-drain output) P0C0-P0C3 : Input/output port (CMOS input/N-ch open-drain output) P0D0-P0D3 : Input/output port (CMOS input/N-ch open-drain output) P0E0-P0E3 : Input/output port (CMOS push-pull output) P1A0 REM RESET VDD XIN, XOUT Note : Input port (CMOS input/N-ch open-drain output)Note : Remote controller output (CMOS push-pull output) : Reset input : Power supply : Resonator connection
Input or output is selected by mask option.
4
Data Sheet U14360EJ1V0DS00
PD17230, 17231, 17232, 17233, 17234, 17235, 17236
BLOCK DIAGRAM
P0A0 P0A1 P0A2 P0A3 RAM 223 x 4 bits P0A RF
Remote Control Divider
REM
8-bit Timer P0B0 P0B1 P0B2 P0B3 P0B SYSTEM REG. Interrupt Controller ALU P0C0 P0C1 P0C2 P0C3 Reset Controller ROM RESET
INT
P0C
PD17230 : 2048 x 16 bits PD17231 : 4096 x 16 bits PD17232 : 6144 x 16 bits PD17233 : 8192 x 16 bits PD17234 : 10240 x 16 bits PD17235 : 12288 x 16 bits PD17236 : 16384 x 16 bits
Instruction Decoder
P0D0 P0D1 P0D2 P0D3
P0D
Program Counter P0E0 P0E1 P0E2 P0E3 Power Supply Circuit Stack (5 levels) CPU Clock VDD GND
P0E
P1A0
Note
P1A
Basic Interval/ Watchdog Timer
XIN OSC XOUT
Note
Input or output selectable by mask option.
Data Sheet U14360EJ1V0DS00
5
PD17230, 17231, 17232, 17233, 17234, 17235, 17236
CONTENTS
1.
PIN FUNCTIONS .......................................................................................................................... 1.1 Pin Function List ............................................................................................................... 1.2 Input/Output Circuits ........................................................................................................ 1.3 Processing of Unused Pins ............................................................................................. MEMORY SPACE ......................................................................................................................... 2.1 Program Counter (PC) ...................................................................................................... 2.2 Program Memory (ROM) .................................................................................................. 2.3 Stack ................................................................................................................................... 2.4 Data Memory (RAM) .......................................................................................................... 2.5 Register File (RF) .............................................................................................................. PORTS .......................................................................................................................................... 3.1 Port 0A (P0A0 through P0A3) ........................................................................................... 3.2 Port 0B (P0B0 through P0B3) ........................................................................................... 3.3 Port 0C (P0C0 through P0C3) ........................................................................................... 3.4 Port 0D (P0D0 through P0D3) ........................................................................................... 3.5 Port 0E (P0E0 through P0E3) ............................................................................................ 3.6 Port 1A (P1A0) .................................................................................................................... 3.7 INT Pin ................................................................................................................................ 3.8 Switching Bit I/O ............................................................................................................... 3.9 Selecting I/O Mode of Group I/O ..................................................................................... 3.10 Specifying Pull-up Resistor Connection ....................................................................... CLOCK GENERATOR CIRCUIT ................................................................................................. 4.1 Instruction Execution Time (CPU Clock) Selection ..................................................... 8-BIT TIMER AND REMOTE CONTROLLER CARRIER GENERATOR CIRCUIT .................. 5.1 Configuration of 8-bit Timer (with modulo function) ................................................... 5.2 Function of 8-bit Timer (with modulo function) ........................................................... 5.3 Carrier Generator Circuit for Remote Controller ......................................................... BASIC INTERVAL TIMER/WATCHDOG TIMER ........................................................................ 6.1 Source Clock for Basic Interval Timer ........................................................................... 6.2 Controlling Basic Interval Timer ..................................................................................... 6.3 Operation Timing for Watchdog Timer .......................................................................... INTERRUPT FUNCTIONS ........................................................................................................... 7.1 Interrupt Sources .............................................................................................................. 7.2 Hardware of Interrupt Control Circuit ............................................................................ 7.3 Interrupt Sequence ........................................................................................................... STANDBY FUNCTIONS ............................................................................................................... 8.1 HALT Mode ......................................................................................................................... 8.2 HALT Instruction Execution Conditions ........................................................................
8 8 10 11 12 12 15 17 19 26 29 29 29 29 29 30 30 31 32 34 35 36 36 37 37 39 41 46 46 46 48 49 49 50 53 55 55 56
2.
3.
4.
5.
6.
7.
8.
6
Data Sheet U14360EJ1V0DS00
PD17230, 17231, 17232, 17233, 17234, 17235, 17236
8.3 8.4 8.5 9. STOP Mode ........................................................................................................................ STOP Instruction Execution Conditions........................................................................ Releasing Standby Mode ................................................................................................. 57 58 58 59 59 59 60
RESET .......................................................................................................................................... 9.1 Reset by Reset Signal Input ............................................................................................ 9.2 Reset by Watchdog Timer (With RESET pin internally pulled down) ....................... 9.3 Reset by Stack Pointer (With RESET pin internally pulled down) ............................
10. LOW-VOLTAGE DETECTOR CIRCUIT (WITH RESET PIN INTERNALLY PULLED DOWN) ................................................................. 11. ASSEMBLER RESERVED WORDS ........................................................................................... 11.1 Mask Option Directives .................................................................................................... 11.2 Reserved Symbols ............................................................................................................ 12. INSTRUCTION SET ..................................................................................................................... 12.1 Instruction Set Outline ..................................................................................................... 12.2 Legend ................................................................................................................................ 12.3 List of Instruction Sets .................................................................................................... 12.4 Assembler (RA17K) Built-In Macro Instruction ............................................................ 13. ELECTRICAL SPECIFICATIONS ................................................................................................ 14. APPLICATION CIRCUIT EXAMPLE ........................................................................................... 15. PACKAGE DRAWINGS .............................................................................................................. 16. RECOMMENDED SOLDERING CONDITIONS .......................................................................... APPENDIX A. DIFFERENCES BETWEEN PD17236 AND PD17P236 ...................................... APPENDIX B. FUNCTIONAL COMPARISON OF PD17236 SUBSERIES RELATED PRODUCTS ....................................................................... APPENDIX C. DEVELOPMENT TOOLS ...........................................................................................
61 62 62 63 70 70 71 72 74 75 81 82 84 85
86 88
Data Sheet U14360EJ1V0DS00
7
PD17230, 17231, 17232, 17233, 17234, 17235, 17236
1. 1.1 PIN FUNCTIONS Pin Function List (1/2)
Symbol P0D0 P0D1 P0D2 P0D3 Function These pins constitute a 4-bit I/O port which can be set in the input or output mode in 4-bit units (group I/O). In the input mode, these pins serve as CMOS input pins with a pull-up resistor, and can be used as key return input lines of a key matrix. The standby status must be released when at least one of the input lines goes low. In the output mode, these pins are used as N-ch open-drain output pins and can be used as the output lines of a key matrix. External interrupt request signal. This signal releases the standby status if an external interrupt request signal is input to it when the INT pin interrupt enable flag (IP) is set. These pins constitute a 4-bit I/O port that can be set in the input or output mode in 1-bit units. In the output mode, this port functions as a high current CMOS output port. In the input mode, function as CMOS input and can be specified to connect pull-up resistor by program. Outputs transfer signal for infrared remote controller. Active-high output. 9 (9) 10 (10) 11 (11) 12 (12) 13 (13) VDD XOUT XIN GND RESET Power supply Connects ceramic resonator for system clock oscillation Output Form N-ch open-drain On Reset Low-level output
Pin No. 27 28 1 2 (28) (29) (1) (2)
3 (3)
INT
-
Input
4 5 6 7
(4) (5) (6) (7)
P0E0 P0E1 P0E2 P0E3
CMOS push-pull
Input
8 (8)
REM
CMOS push-pull - -
Low-level output - (Oscillation stops) - Input
Ground Turns ON pull down resistor if POC or watchdog timer overflows and if the stack pointer overflows or underflows, and resets the system. Usually, the pull-down resistor is ON. This can be set in the input or output mode by mask option. In the input mode, it serves as a CMOS input pin. However, it cannot release the STOP mode. In the output mode, this pin functions as an N-ch open-drain output pin and can be used as an output line for a key matrix.
- -
14 (14)
P1A0
- (Input)
Input
N-ch open-drain (Output) -
Highimpedance output Input
15 16 17 18 19 20 21 22
(16) (17) (18) (19) (20) (21) (22) (23)
P0A0 P0A1 P0A2 P0A3 P0B0 P0B1 P0B2 P0B3
These pins are CMOS input pins with a 4-bit pull-up resistor. They can be used as the key return input lines of a key matrix. If any one of these pins goes low, the standby status is released.
These pins constitute a 4-bit I/O port that can be set in the input or output mode in 1-bit units. In the input mode, these pins are CMOS input pins with a pull-up resistor, and can be used as the key return input lines of a key matrix. The standby status is released when at least one of these pins goes low. In the output mode, they serve as N-ch open-drain output pins and can be used as the output lines of a key matrix.
N-ch open-drain
Input
Remark The number in parenthesis in the Pin No. column indicates the pin numbers of the 30-pin plastic SSOP.
8
Data Sheet U14360EJ1V0DS00
PD17230, 17231, 17232, 17233, 17234, 17235, 17236
1.1 Pin Function List (2/2)
Symbol P0C0 P0C1 P0C2 P0C3 Function These pins constitute a 4-bit I/O port that can be set in the input or output mode in 4-bit units (group I/O). In the input mode, these pins are CMOS input pins with a pull-up resistor, and can be used as the key return input lines of a key matrix. The standby status is released when at least one of these pins goes low. In the output mode, they serve as N-ch open-drain output pins and can be used as the output lines of a key matrix. These pins cannot be used. Leave open. Output Form N-ch open-drain On Reset Low-level output
Pin No. 23 24 25 26 (24) (25) (26) (27)
(15) (30)
IC1 IC2
-
-
Remark The number in parenthesis in the Pin No. column indicates the pin numbers of the 30-pin plastic SSOP.
Data Sheet U14360EJ1V0DS00
9
PD17230, 17231, 17232, 17233, 17234, 17235, 17236
1.2 Input/Output Circuits
The equivalent input/output circuit for each PD17236 pin is shown below. (1) P0A
VDD
(Mask option) Input buffer (Mask option) N-ch (Mask option)
(4) P1A

Input buffer
Data
Output latch
(2) P0B, P0C, P0D
(Mask option)
VDD
Remark * When set to input by mask option
P-ch
 SW: OFF, SW: ON * When set to output by mask option SW: ON, SW: OFF (5) RESET
VDD
Data
Output latch
Output disable Selector
N-ch
Reset input
P-ch
Input buffer
(3) P0E
VDD
Input buffer Schmitt trigger input with hysteresis characteristics N-ch
Data
Pull-up register VDD
P-ch
(6) INT
Data
Output latch
P-ch
Input buffer
Output disable
N-ch
Schmitt trigger input with hysteresis characteristics
Selector
(7) REM
Input buffer
VDD Data P-ch
Output disable
N-ch
10
Data Sheet U14360EJ1V0DS00
PD17230, 17231, 17232, 17233, 17234, 17235, 17236
1.3 Processing of Unused Pins
Process the unused pins as follows: Table 1-1. Processing of Unused Pins
Pin P0A0-P0A3 P0B0-P0B3 P0C0-P0C3 P0D0-P0D3 P0E0-P0E3 Input: Individually connect to VDD or GND via resistor. Output: Leave unconnected. Connect to GND. Leave unconnected. Connect to GND. These pins cannot be used. Leave unconnected. Recommended Connection Leave unconnected.
P1A0 REM INT IC1, IC2
Data Sheet U14360EJ1V0DS00
11
PD17230, 17231, 17232, 17233, 17234, 17235, 17236
2. 2.1 MEMORY SPACE Program Counter (PC)
The program counter (PC) specifies an address of the program memory (ROM). The program counter is an 11/12/13-bit binary counter and a 1-bit segment counter (SGR) as shown in Figure 2-1. Its contents are initialized to address 0000H at reset. Figure 2-1. Configuration of Program Counter
Page MSB SGR PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 LSB PC0
PC (PD17230) PC (PD17231) PC (PD17232, 17233) PC (PD17234, 17235, 17236)
2.1.1
Segment register (SGR)
The segment register specifies a segment of the program memory. Table 2-1 shows the relation between the segment register and program memory. Table 2-1. Relation between Segment Register and Program Memory
Value of Segment Register 0 1 Segment of Program Memory Segment 0 Segment 1
The segment register is set when the following instructions are executed: * BR @AR * CALL @AR * SYSCAL entry
12
Data Sheet U14360EJ1V0DS00
PD17230, 17231, 17232, 17233, 17234, 17235, 17236
The first address of the subroutine that can be called by the system call instruction ("SYSCAL entry") is the first 16 steps of each block (block 0 to 7) in page 0 of segment 1 (system segment). Figure 2-2. Outline of System Call Instruction
Segment 0 00000H 02000H
Segment 1 (system segment) 02000H Block 0 0 2 0FFH 02100H Block 1 0 2 1FFH 02200H Block 2 0 2 0 0FH
Block 0 of segment 1 Entry address of SYSCAL instruction
Page 0 (16 bits x 2K steps)
0 2 2FFH . . . . 02700H Block 7
Area in which entry address of system segment can be specified
0 0 7FFH 00800H Page 1 0 0FFFH 01000H Page 2 0 1 7FFH 01800H Page 3 0 1FFFH (16 bits x 8K steps)
0 2 7FFH 02800H Page 1 0 2FFFH 03000H Page 2 0 3 7FFH 03800H Page 3 0 3FFFH (16 bits x 8K steps)
Data Sheet U14360EJ1V0DS00
13
PD17230, 17231, 17232, 17233, 17234, 17235, 17236
Figure 2-3. Value of Program Counter on Execution of Each Instruction
Program Counter Instruction BR addr Page 0 Page 1 Page 2 Page 3 CALL addr
Retained Retained
Contents of Program Counter (PC)Note SGR b12 0 0 1 1 0 b11 0 1 0 Operand of instruction (addr) 1 0 Operand of instruction (addr) b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
SYSCAL entry 1 BR @AR CALL @AR Contents of address register MOVT DBF, @AR RET RETSK RETI Other instructions (including skip instruction) On acknowledging interrupt 0 Vector address of each interrupt
Retained
0
0
entryH
0
0
0
0
entryL
Contents (return address) of address stack register (ASR) specified by stack pointer (SP)
Increment
Watchdog timer reset, RESET pin, reset by stack pointer 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Note
PD17230 PD17231 PD17232, 17233
: b0 through b10 : b0 through b11 : b0 through b12
PD17234, 17235, 17236 : b0 through b12, SGR
Remark entryH : High-order 3 bits of entry entryL : Low-order 4 bits of entry Table 2-2. Interrupt Vector Address
Priority 1 2 3 Internal/External Internal External Internal Interrupt Source 8-bit timer Rising and falling edges of INT pin Basic interval timer 0003H 0002H 0001H Vector Address
14
Data Sheet U14360EJ1V0DS00
PD17230, 17231, 17232, 17233, 17234, 17235, 17236
2.2 Program Memory (ROM)
The configuration of the program memory is as follows:
Part Number Program Memory Capacity 2048 x 16 bits 4096 x 16 bits 6144 x 16 bits 8192 x 16 bits 10240 x 16 bits 12288 x 16 bits 16384 x 16 bits Program Memory Address 0000H-07FFH 0000H-0FFFH 0000H-17FFH 0000H-1FFFH 0000H-27FFH 0000H-2FFFH 0000H-3FFFH
PD17230 PD17231 PD17232 PD17233 PD17234 PD17235 PD17236
The program memory stores a program, interrupt vector table, and fixed data table. The program memory is addressed by the program counter. Figure 2-4 shows the program memory map. The entire range of the program memory can be addressed by the BD addr, BR @AR, CALL @AR, MOVT DBF, and @AR instructions. Note, however, that the subroutine entry addresses that can be specified by the CALL addr instruction are from 0000H to 07FFH.
Data Sheet U14360EJ1V0DS00
15
PD17230, 17231, 17232, 17233, 17234, 17235, 17236
Figure 2-4. Program Memory Map
Address 0 0 0 0 H Reset start address 0 0 0 1 H Basic interval timer interrupt vector 0 0 0 2 H INT pin rising/falling edge interrupt vector 0 0 0 3 H 8-bit timer interrupt vector 0 7 FFH ( PD17230) Segment 0 Branch addresses for BR addr Page 1 instruction Page 2 1 7 FFH ( PD17232) Page 3 1 FFFH 2000H ( PD17233) Page 0 ( PD17234) Page 1 2 FFFH ( PD17235) Segment 1 Branch (system addresses segment) for BR addr Page 2 instruction Subroutine entry address for CALL addr instruction Page 0 Subroutine entry Branch addresses for address for CALL BR@AR instruction addr instruction Subroutine entry addresses for CALL@AR instruction Table reference addresses for MOVT DBF, @AR instruction
0 FFFH
( PD17231)
2 7 FFH
Page 3 3 FFFH ( PD17236) 16 bits
16
Data Sheet U14360EJ1V0DS00
PD17230, 17231, 17232, 17233, 17234, 17235, 17236
2.3 Stack
A stack is a register to save a program return address and the contents of system registers (to be described later) when a subroutine is called or when an interrupt is accepted. 2.3.1 Stack configuration
Figure 2-5 shows the stack configurarion. A stack consists of a stack pointer (a 4-bit binary counter, the high-order 1 bit fixed to 0), five 11-bit (PD17230)/ 12-bit (PD17231)/13-bit (PD17232, 17233)/14-bit (PD17234, 17235, 17236) address stack registers, and three 6-bit interrupt stack registers. Figure 2-5. Stack Configuration
Stack pointer (SP) b3 0 b2 b1 b0 0H 1H 2H 3H 4H 5H The RESET pin is internally pulled down and reset is effected. 6H 7H b13 b12 b11 b10 b9
Address stack registers (ASR) b8 b7 b6 b5 b4 b3 b2 b1 b0
SPb2 SPb1 SPb0
Address stack register 0 Address stack register 1 Address stack register 2 Address stack register 3 Address stack register 4 Undefined Undefined Undefined
PD17230 PD17231 PD17232, 17233 PD17234, 17235, 17236
Interrupt stack registers (INTSK) b5 0H BANKSK0 1H 2H BANKSK1 BANKSK2 b4 BCDSK0 BCDSK1 BCDSK2 b3 CMPSK0 CMPSK1 CMPSK2 b2 CYSK0 CYSK1 CYSK2 b1 ZSK0 ZSK1 ZSK2 b0 IXESK0 IXESK1 IXESK2
Data Sheet U14360EJ1V0DS00
17
PD17230, 17231, 17232, 17233, 17234, 17235, 17236
2.3.2 Function of stack
The address stack register stores a return address when the subroutine call instruction or table reference instruction (first instruction cycle) is executed or when an interrupt is accepted. It also stores the contents of the address registers (ARs) when a stack manipulation instruction (PUSH AR) is executed. If subroutines or interrupts are nested to more than 5 levels, the RESET pin is internally pulled down and a reset is effected. The interrupt stack register (INTSK) saves the contents of the bank register (BANK) and program status word (PSWORD) when an interrupt is accepted. The saved contents are restored when an interrupt return (RETI) instruction is executed. INTSK saves data each time an interrupt is accepted, but the data stored first is lost if more than 3 levels of interrupts occur. 2.3.3 Stack Pointer (SP) and Interrupt Stack Pointer
Table 2-3 shows the operations of the stack pointer (SP). The stack pointer can take eight values, 0H-07. Because there are only five stack registers available, however, the RESET pin is internally pulled down and reset is effected if the value of SP is 6 or greater. Table 2-3. Operations of Stack Pointer
Instruction CALL addr CALL @AR MOVT DBF, @AR (1st Instruction Cycle) PUSH AR SYSCAL entry When interrupt is accepted RET RETSK MOVT DBF, @AR (2nd Instruction Cycle) POP AR RETI +1 +1 +1 0 -1 -1 -1 0 Value of Stack Pointer (SP) Counter of Interrupt Stack Register
18
Data Sheet U14360EJ1V0DS00
PD17230, 17231, 17232, 17233, 17234, 17235, 17236
2.4 Data Memory (RAM)
Data memory (random access memory) stores data for operations and control. It can be read-/write-accessed by instructions. 2.4.1 Memory configuration
Figure 2-6 shows the configuration of the data memory (RAM). The data memory consists of two "banks": BANK0 and BANK1. In each bank, every 4 bits of data is assigned an address. The high-order 3 bits of the address indicate a "row address" and the low-order 4 bits of the address indicate a "column address". For example, a data memory location indicated by row address 1H and column address 0AH is termed a data memory location at address 1AH. Each address stores data of 4 bits (= a "nibble"). In addition, the data memory is divided into following six functional blocks: (1) System register (SYSREG) A system register (SYSREG) is resident on addresses 74H to 7FH (12 nibbles long) of each bank. In other nibbles, each bank has a system register at its addresses 74H to 7FH. (2) Data buffer (DBF) A data buffer is resident on addresses 0CH to 0FH (4 nibbles long) of bank 0 of data memory. The reset value is 0320H. (3) General register (GR) A general register is resident on any row (16 nibbles long) of any bank of data memory. The row address of the general register is pointed by the general pointer (RP) in the system register (SYSREG). (4) Port register A port data register is resident on addresses 6FH, and 70H to 73H (5 nibbles) of BANK0 of data memory. No data can be written to or read from the addresses 71H to 73H of BANK1.
Data Sheet U14360EJ1V0DS00
19
PD17230, 17231, 17232, 17233, 17234, 17235, 17236
(5) General-purpose data memory The general-purpose data memory area is an area of the data memory excluding the system register area, and the port register areayI This memory area has a total of 223 nibbles (111 nibbles in BANK0 and 112 nibbles in BANK1). Figure 2-6. Configuration of Data Memory
Column address 0 0 1 2 3 4 5 6 7
BANK 0 8 9 A B C D E F
Data buffer (DBF)
Row address
1 2 3 4 5 6 7 P0A P0B P0C P0D System register (SYSREG) P0E Example Address 1AH in BANK 0
0 0
1
Column address 2 3 4 5
6
BANK 1 7 8
9
A
B
C
D
E
F
Row address
1 2 3 4 5 6 7 P1A
Note 2 Note 1
System register (SYSREG)
Notes 1. Address 6FH of bank 1 can be used as a general-purpose data memory area. 2. Only bit 0 of address 70H of bank 1 is used. Bits 1 through 3 are fixed to 0. Caution No data can be written to or read from the addresses 71H to 73H of BANK1.
20
Data Sheet U14360EJ1V0DS00
PD17230, 17231, 17232, 17233, 17234, 17235, 17236
2.4.2 System registers (SYSREG)
The system registers are registers that are directly related to control of the CPU. These registers are mapped to addresses 74H-7FH on the data memory and can be referenced regardless of bank specification. The system registers include the following registers: * Address registers (AR0-AR3) * Window register (WR) * Bank register (BANK) * Memory pointer enable flag (MPE) * Memory pointers (MPH, MPL) * Index registers (IXH, IXM, IXL) * General register pointers (RPH, RPL) * Program status word (PSWORD) Figure 2-7. Configuration of System Register
Address
74H
75H
76H
77H
78H
79H
7AH
7BH Index register (IX)
7CH
7DH General register pointer (RP)
7EH
7FH Program status word (PSWORD)
Name
Address register (AR)
Window Bank register register (WR) (BANK)
Data memory row address pointer (MP) IXH MPH IXM MPL IXL
Symbol Bit
AR 3
AR 2
AR 1
AR 0
WR
BANK
RPH
RPL
PSW
b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 00 (AR) ( PD17234,17235,17236) (AR) ( PD17232,17233) (AR) ( PD17231) (AR) ( PD17230) (WR) (BANK) M 000 P000 E (IX) 000 (MP) (RP) I BCC CMY Z X E DP
Data
000 0000
00000 Initial Value At Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Undefined 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Data Sheet U14360EJ1V0DS00
21
PD17230, 17231, 17232, 17233, 17234, 17235, 17236
2.4.3 General register (GR)
A general register is a 16-word register on the data memory and used for arithmetic operations and transfer of data to and from the data memory. (1) Configuration of general register Figure 2-8 shows the configuration of the general register. A general register occupies 16 nibbles (16 x 4 bits) on a selected row address of the data memory as shown in Figure 2-6. The row address is selected by the general register pointer (RP) of the system register. The RP having four significant bits can point to any row address in the range of 0H to 7H of each bank (BANK0 and BANK1). (2) Functions of the general register The general register enables an arithmetic operation and data transfer between the data memory and a selected general register by a single instruction. As a general register is a part of the data memory, you can say that the general register enables arithmetic operation and data transfer between two locations of the data memory. Similarly, the general register can be accessed by a data memory manipulation instruction as it is a part of the data memory. Figure 2-8. Configuration of General Registers
General register pointer (RP) RPH RPL BANK0 0 0 1 A s s i g n e d t o 2 3 4 5 6 7 Port register BANK1 System registers RP
Port register
Column address 2 3 4 5 6 7 8 9 A B C D E F
b 3 b 2 b 1 b 0 b3 b2 b1 b 0 F i x e d t o 0 F i x e d t o 0 F i x e d t o 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1
1
General registers (16 nibbles)
Example General registers when RP = 0000010B
General register settable range
1 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
0 B C1 D 2 f 3 l a4 g5 6 7 System registers Same system registers exist
22
Data Sheet U14360EJ1V0DS00
PD17230, 17231, 17232, 17233, 17234, 17235, 17236
2.4.4 Data buffer (DBF)
The data buffer on the addresses 0CH to 0FH of data memory is used for data transfer to and from peripheral hardware and for storage of data during table reference. (1) Functions of the data buffer The data buffer has two major functions: a function to transfer to and from hardware and a function to read constant data from the program memory (for table reference). Figure 2-9 shows the relationship between the data buffer and peripheral hardware. Figure 2-9. Data Buffer and Peripheral Hardware
Data buffer (DBF)
Peripheral address Internal bus 05H, 06H
Peripheral hardware 8-bit timer (TMC, TMM) Carrier generator for remote controller (NRZLTMM, NRZHTMM) Address register (AR)
03H, 04H
40H Program memory (ROM) Constant data
Data Sheet U14360EJ1V0DS00
23
PD17230, 17231, 17232, 17233, 17234, 17235, 17236
Table 2-4. Relations between Hardware Peripherals and Data Buffer
Hardware Peripherals 8-bit timer Name 8-bit counter 8-bit modulo register Remote controller carrier generator NRZ low-level timer modulo register NRZ high-level timer modulo register Peripheral Register Transferring Data with Data Buffer Symbol TMC TMM Peripheral address Data buffer used 05H 06H DBF0, DBF1 DBF0, DBF1 PUT/GET GET only PUT only
NRZLTMM
03H
DBF0, DBF1
PUT GET
NRZHTMM
04H
DBF0, DBF1
PUT (clear bit 3 of DBF1 to 0) GET (bits 3 of DBF1 is always 0) PUTNote 1 GETNote 2
Address register
Address register
AR
40H
DBF0-DBF3
Notes 1. In the PD17230: bits 0 to 3 of AR3 and bit 3 of AR2 are any, in the PD17231: bits 0 to 3 of AR3 are any, in the PD17232, 17233: bits 1 to 3 of AR3 are any, in the PD17234, 17235, 17236: bits 2 to 3 of AR3 are any 2. In the PD17230: bits 0 to 3 of AR3 and bit 3 of AR2 are always 0, in the PD17231: bits 0 to 3 of AR3 are always 0, in the PD17232, 17233: bits 1 to 3 of AR3 are always 0, in the PD17234, 17235, 17236: bits 2 to 3 of AR3 are always 0 (2) Table reference A MOVT instruction reads constant data from a specified location of the program memory (ROM) and sets it in the data buffer. The function of the MOVT instruction is explained below. MOVT DBF, @AR: Reads data from a program memory location pointed to by the address register (AR) and sets it in the data buffer (DBF).
Data buffer DBF 3 DBF 2 DBF 1 DBF 0
Program memory (ROM) MOVT DBF, @ AR
16 bits b15 b0
24
Data Sheet U14360EJ1V0DS00
PD17230, 17231, 17232, 17233, 17234, 17235, 17236
(3) Note on using data buffer When transferring data to/from the peripheral hardware via the data buffer, the unused peripheral addresses, write-only peripheral registers (only when executing PUT), and read-only peripheral registers (only when executing GET) must be handled as follows: * When device operates Nothing changes even if data is written to the read-only register. If the unused address is read, an undefined value is read. Nothing changes even if data is written to that address. * Using assembler An error occurs if an instruction is executed to read a write-only register. Again, an error occurs if an instruction is executed to write data to a read-only register. An error also occurs if an instruction is executed to read or write an unused address. * If an in-circuit emulator (IE-17K or IE-17K-ET) is used (when instruction is executed for patch processing) An undefined value is read if an attempt is made to read the data of a write-only register, but an error does not occur. Nothing changes even if data is written to a read-only register, and an error does not occur. An undefined value is read if an unused address is read; nothing changes even if data is written to this address. An error does not occur.
Data Sheet U14360EJ1V0DS00
25
PD17230, 17231, 17232, 17233, 17234, 17235, 17236
2.5 Register File (RF)
The register file mainly consists of registers that set the conditions of the peripheral hardware. These registers can be controlled by dedicated instructions PEEK and POKE, and the embedded macro instructions of RA17K, SETn, CLRn, and INITFLG. 2.5.1 Configuration of register file
Figure 2-10 shows the configuration of the register file and how the register file is accessed by the PEEK and POKE instructions. The control registers are controlled by using dedicated instructions PEEK and POKE. Since the control registers are assigned to addresses 00H-3FH regardless of the bank, the addresses 00H-3FH of the general-purpose data memory cannot be accessed when the PEEK or POKE instruction is used. The addresses that can be accessed by the PEEK and POKE instructions are the addresses 00H-3FH of the control registers and 40H-7FH of the general-purpose data memory. The register file consists of these addresses. The control registers are assigned to addresses 80H-BFH on the IE-17K to facilitate debugging. Figure 2-10. Register File Access with PEEK or POKE Instructions
Column address 6 7 8 9
0 0 1 2 3 4 5 6 7 Row address
1
2
3
4
5
A
B
C
D
E
F
Data memory
POKE M063, WR
System register
0 1 2 POKE LCDMD, WR 3 Register file Control register PEEK WR, SP
26
Data Sheet U14360EJ1V0DS00
PD17230, 17231, 17232, 17233, 17234, 17235, 17236
2.5.2 Control registers
The control registers consists of a total of 64 nibbles (64 x 4 bits) of the addresses 00H-3FH of the register file. Of these, however, only 16 nibbles are actually used. The remaining 48 nibbles are unused registers that are inhibited from being read or written. When the "PEEK WR, rf" instruction is executed, the contents of the register file addressed by "rf" are read to the window register. When the "POKE rf, WR" instruction is executed, the contents of the window register are written to the register file addressed by "rf". When using the assembler (RA17K), the macro instructions listed below, which are embedded as flag type symbol manipulation instructions, can be used. The macro instructions allow the contents of the register file to be manipulated in bit units. For the configuration of the control register, refer to Figure 11-1 Register File List. SETn CLRn SKTn SKFn NOTn INITFLG : Sets flag to "1" : Sets flag to "0" : Skips if all flags are "1" : Skips if all flags are "0" : Complements flag : Initializes flag
INITFLGX : Initalizes flag 2.5.3 Notes on using register files
When using the register files, bear in mind the points described below. For details, refer to PD172xx subseries User's Manual (U12795E). (1) When manipulating control registers (read-only and unused registers) When manipulating the write-only (W), the read-only (R) and unused control registers by using the assembler or in-circuit emulator, keep in mind the following points: * When device operates Nothing changes even if data is written to the read-only register. If the unused register is read, an undefined value is read; nothing is changed even if data is written to this register. * Using assembler An error occurs if instruction is excecuted to read data to the write-only register. An error occurs if an instruction is executed to write data to the read-only register. An error also occurs if an instruction is executed to read or write the unused address. * When an in-circuit emulator (IE-17K or IE-17K-ET) is used (when instruction is executed for patch processing) An undefined value is read if the write-only register is read, and an error does not occur. Nothing changes even if data is written to the read-only register, and an error does not occur. An undefined value is read if the unused address is read; nothing changes even if data is written to this address. An error does not occur.
Data Sheet U14360EJ1V0DS00
27
PD17230, 17231, 17232, 17233, 17234, 17235, 17236
(2) Symbol definition of register file An error occurs if a register file address is directly specified as a numeral by the operand "rf" of the "PEEK WR, rf" or "POKE rf, WR" instruction if the 17K Series Assembler (RA17K) is being used. Therefore, the addresses of the register file must be defined in advance as symbols. To define the addresses of the control registers as symbols, define them as the addresses 80H-BFH of BANK0. The portion of the register file overlapping the data memory (40H-7FH), however, can be defined as symbols as is.
28
Data Sheet U14360EJ1V0DS00
PD17230, 17231, 17232, 17233, 17234, 17235, 17236
3. 3.1 PORTS Port 0A (P0A0 through P0A3)
This is a 4-bit input port. Data is read through port register P0A (address 70H of BANK0). This port is a CMOS input port with a pull-up resistor, and can be used for key return input for a key matrix. In the standby mode, the standby status is released when a low level is input to at least one of these pins.
3.2
Port 0B (P0B0 through P0B3)
This is a 4-bit I/O port which can be set in the input or output mode in 1-bit units by using P0BBIO (address 26H) of the register file. In the input mode, each bit of this port serves as a CMOS input pin with a pull-up resistor and can be used as a key return input line of a key matrix. In the standby mode, the standby status is released when a low level is input to at least one of these pins. In the output mode, these pins serve as N-ch open-drain output pins and can be used as key source lines of a key matrix. The data input to this port can be read or the data output from this port can be set by using the P0B register (address 71H of BANK0). When this port is read in the output mode, the contents of the output latch are read. In the input mode, a pull-up resistor of 200 k is connected to each bit of this port. In the output mode, the pullup resistor is disconnected. On reset, this port is set in the input mode.
3.3
Port 0C (P0C0 through P0C3)
This is a 4-bit I/O port which can be set in the input or output mode in 4-bit units (group I/O) by using P0CDGIO (bit 2 of address 37H) of the register file. In the input mode, each bit of this port serves as a CMOS input pin with a pull-up resistor and can be used as a key return input line of a key matrix. In the standby mode, the standby status is released when a low level is input to at least one of these pins. In the output mode, these pins serve as N-ch open-drain output pins and can be used as key source lines of a key matrix. The data input to this port can be read or the data output from this port can be set by using the P0C register (address 72H of BANK0). When this port is read in the output mode, the contents of the output latch are read. In the input mode, a pull-up resistor of 200 k is connected to each bit of this port. In the output mode, the pullup resistor is disconnected. On reset, this port is set in the output mode and outputs low.
3.4
Port 0D (P0D0 through P0D3)
This is a 4-bit I/O port which can be set in the input or output mode in 4-bit units (group I/O) by using P0CDGIO (bit 3 of address 37H) of the register file. In the input mode, each bit of this port serves as a CMOS input pin with a pull-up resistor and can be used as a key return input line of a key matrix. In the standby mode, the standby status is released when a low level is input to at least one of these pins. In the output mode, these pins serve as N-ch open-drain output pins and can be used as key source lines of a key matrix. The data input to this port can be read or the data output from this port can be set by using the P0D register (address 73H of BANK0). When this port is read in the output mode, the contents of the output latch are read. In the input mode, a pull-up resistor of 200 k is connected to each bit of this port. In the output mode, the pullup resistor is disconnected. On reset, this port is set in the output mode and outputs low.
Data Sheet U14360EJ1V0DS00
29
PD17230, 17231, 17232, 17233, 17234, 17235, 17236
3.5 Port 0E (P0E0 through P0E3)
This is a 4-bit I/O port which can be set in the input or output mode in 1-bit units by the P0EBIO (address 27H) of the register file. To read the input data or to set the output data, use the P0E register (address 6FH of BANK0). When data is read in the output mode, the contents of the output latch are read. Connection of a pull-up resistor can be specified in 1-bit units by the P0EBPU (address 17H) of the register file. (When the pull-up resistor is connected, note that the pull-up resistor is not disconnected even when the output mode is set.) On reset, this port is set in the input port.
3.6
Port 1A (P1A0)
This port can be set in the input or output mode by mask option. In the input mode, this port serves as a CMOS input port. The input data is read by using port register P1A (address 70H of BANK1). This port cannot be used to release the STOP mode. In the output mode, it serves as an N-ch open-drain output port and can be used as a key source line of a key matrix. The output data is set by using port register P1A (address 70H of BANK1). When this port is read in the output mode, the contents of the output latch are read. On reset, this port goes into a high-impedance state.
30
Data Sheet U14360EJ1V0DS00
PD17230, 17231, 17232, 17233, 17234, 17235, 17236
3.7 INT Pin
This pin inputs an external interrupt request signal. At either the rising or falling edge of the signal input to this pin, the IRQ flag (RF: address 3EH, bit 0) is set. The status of this pin can be read by using the INT flag (RF: address 0FH, bit 0). When the high level is input to the pin, the INT flag is set to "1"; when the low level is input, the flag is reset to "0" (refer to 7.2.1 INT). Figure 3-1. Relations between Port Register and Each Pin
Bank Address Target Port Bit Output Format 0 70H Port 0A b3 b2 b1 b0 71H Port 0B b3 b2 b1 b0 72H Port 0C b3 b2 b1 b0 73H Port 0D b3 b2 b1 b0 6FH Port 0E b3 b2 b1 b0 1 70H Port 1A (input/output mode set by mask option) b0 P0A3 P0A2 P0A1 P0A0 P0B3 P0B2 P0B1 P0B0 P0C3 P0C2 P0C1 P0C0 P0D3 P0D2 P0D1 P0D0 P0E3 P0E2 P0E1 P0E0 P1A0 Input (in input mode) N-ch open drain (in output mode) - - - - Input mode (without pullup resistor) CMOS push-pull Input mode (without pullup resistor) Output mode (low-level output) N-ch open drain Output latch Output latch Output latch Input Read Contents Written Contents On Reset
Input mode Output mode Input mode Output mode Pin status - - - Input mode (with pull-up resistor)
Output latch Output latch Output latch Output mode (highimpedance output)
Data Sheet U14360EJ1V0DS00
31
PD17230, 17231, 17232, 17233, 17234, 17235, 17236
3.8 Switching Bit I/O
The I/O which can be set in the input or output mode in bit units is called a bit I/O. P0B and P0E are bit I/O ports, which can be set in the input or output mode in bit units by the register file shown below. When the mode is changed from input to output, the P0B and P0E output latch contents are output to the port lines, as soon as the mode has been changed.
3 P0BBIO3
2 P0BBIO2
1 P0BBIO1
0 P0BBIO0
Address RF : 26H
On reset 0H
R/W R/W
P0BBIO0 0 1
Sets P0B0 Input/Output Mode Sets P0B0 in input mode Sets P0B0 in output mode
P0BBIO1 0 1
Sets P0B1 Input/Output Mode Sets P0B1 in input mode Sets P0B1 in output mode
P0BBIO2 0 1
Sets P0B2 Input/Output Mode Sets P0B2 in input mode Sets P0B2 in output mode
P0BBIO3 0 1
Sets P0B3 Input/Output Mode Sets P0B3 in input mode Sets P0B3 in output mode
32
Data Sheet U14360EJ1V0DS00
PD17230, 17231, 17232, 17233, 17234, 17235, 17236
3 P0EBIO3 2 P0EBIO2 1 P0EBIO1 0 P0EBIO0 Address RF : 27H On reset 0H R/W R/W
P0EBIO0 0 1
Sets P0E0 Input/Output Mode Sets P0E0 in input mode Sets P0E0 in output mode
P0EBIO1 0 1
Sets P0E1 Input/Output Mode Sets P0E1 in input mode Sets P0E1 in output mode
P0EBIO2 0 1
Sets P0E2 Input/Output Mode Sets P0E2 in input mode Sets P0E2 in output mode
P0EBIO3 0 1
Sets P0E3 Input/Output Mode Sets P0E3 in input mode Sets P0E3 in output mode
Data Sheet U14360EJ1V0DS00
33
PD17230, 17231, 17232, 17233, 17234, 17235, 17236
3.9 Selecting I/O Mode of Group I/O
An I/O that is set in the input or output mode in 4-bit units is called a group I/O. P0C and P0D can be used as group I/O ports. The input and output modes of these ports are selected by using the following register file. If the mode is changed from input to output, the contents of the port register are output to the respective ports as soon as the mode has been changed.
3 P0DGIO
2 P0CGIO
1 0
0 0
Address RF : 37H
On reset CH
R/W R/W
P0CGIO 0 1
I/O mode of P0C0-P0C3 Sets P0C0-P0C3 in input mode. Sets P0C0-P0C3 in output mode.
P0DGIO 0 1
I/O mode of P0D0-P0D3 Sets P0D0-P0D3 in input mode. Sets P0D0-P0D3 in output mode.
34
Data Sheet U14360EJ1V0DS00
PD17230, 17231, 17232, 17233, 17234, 17235, 17236
3.10 Specifying Pull-up Resistor Connection
Whether or not a pull-up resistor is connected to port P0E can be specified by the following registers of the register file in 1-bit unitsNote.
3 2 1 0 Address RF : 17H On reset 0H R/W R/W
P0EBPU3 P0EBPU2 P0EBPU1 P0EBPU0
P0EBPU0 Connects Pull-Up Resistor to P0E0 0 1 Not connected Connected
P0EBPU1 Connects Pull-Up Resistor to P0E1 0 1 Not connected Connected
P0EBPU2 Connects Pull-Up Resistor to P0E2 0 1 Not connected Connected
P0EBPU3 Connects Pull-Up Resistor to P0E3 0 1 Not connected Connected
Note
To disconnect the pull-up resistor in the output mode, clear the corresponding bit of the P0EBPU register.
Data Sheet U14360EJ1V0DS00
35
PD17230, 17231, 17232, 17233, 17234, 17235, 17236
4. 4.1 CLOCK GENERATOR CIRCUIT Instruction Execution Time (CPU Clock) Selection
The PD17236 is equipped with a clock oscillator that supplies clocks to the CPU and hardware peripherals. Instruction execution time can be changed in two steps (ordinary mode and high-speed mode) without changing the oscillation frequency. To change the instruction execution time, change the mode of SYSCK (RF: address 02H) of the register file by using the POKE instruction. Note, that the mode is actually only changed when the instruction next to the POKE instruction has been executed. When using the high-speed mode, pay attention to the supply voltage. (Refer to 13. ELECTRICAL SPECIFICATIONS.) On reset, the ordinary mode is set.
3 0 2 0 1 0 0 SYSCK Address RF : 02H On reset 0H R/W R/W
SYSCK 0 1
Selects Instruction Execution Time Ordinary mode 32/fX (8 s) High-speed mode 16/fX (4 s)
Figures in ( ): indicate figures when system clock fX = 4 MHz.
36
Data Sheet U14360EJ1V0DS00
PD17230, 17231, 17232, 17233, 17234, 17235, 17236
5. 8-BIT TIMER AND REMOTE CONTROLLER CARRIER GENERATOR CIRCUIT
The PD17236 is equipped with the 8-bit timer which is mainly used to generate the leader pulse of the remote controller signal, and to output codes.
5.1
Configuration of 8-bit Timer (with modulo function)
Figure 5-1 shows the configuration of the 8-bit timer. As shown in this figure, the 8-bit timer consists of an 8-bit counter (TMC), an 8-bit modulo register (TMM), a comparator that compares the value of the timer with the value of the modulo register, and a selector that selects the operation clock of the 8-bit timer. To start/stop the 8-bit timer, and to reset the 8-bit counter, TMEN (address 33H, bit 3) and TMRES (address 33H, bit 2) of the register file are used. To select the operation clock of the 8-bit timer, use TMCK1 (address 33H, bit 1) and TMCK0 (address 33H, bit 0) of the register file. The value of the 8-bit counter is read by using the GET instruction through DBF (data buffer). No value can be set to the 8-bit counter. A value is set to the modulo register by using the PUT instruction through DBF. The value of the modulo register cannot be read. When the value of the counter coincides with that of the modulo register, an interrupt flag (IRQTM: address 3FH, bit 0) of the register file is set.
TMC
7 6 5 4 3 2 1 0 Address Peripheral register: 05H On reset 00H R/W R
8-bit counter
TMM
7 6 5 4 3 2 1 0 Address Peripheral register: 06H On reset FFH R/W W
8-bit modulo register
Caution Do not clear TMM to 0 (IRQTM is not set).
Data Sheet U14360EJ1V0DS00
37
PD17230, 17231, 17232, 17233, 17234, 17235, 17236
Figure 5-1. Configuration of 8-bit Timer and Remote Controller Carrier Generator Circuit
Data buffer
Internal bus 8-bit timer
RF : 33H TMEN TMRES TMCK1 TMCK0
fX/32 fX/64 fX/256 Selector
8-bit modulo register TMM
Comparator
IRQTM
R S
Q 8-bit counter TMC
Remote controller carrier generator circuit fX/2Note fXNote SW 7-bit counter RF : 11H Comparator bit 7 x 7-bit modulo register NRZLTMM NRZ NRZBF RF : 12H
7-bit counter
Comparator bit 7 0 fixed 7-bit modulo register NRZHTMM
REM
Note
Mask options. Select either one of these.
Remark TMM, TMC, NRZLTMM, and NRZHTMM are peripheral registers.
38
Data Sheet U14360EJ1V0DS00
PD17230, 17231, 17232, 17233, 17234, 17235, 17236
5.2 Function of 8-bit Timer (with modulo function)
3 TMEN 2 TMRES 1 TMCK1 0 TMCK0 Address RF : 33H On reset 8H
Note 1
R/W R/W
Note 2
TMCK1 0
TMCK0 0
8-Bit Timer Clock Source Selection Count clock: fX/32 (measurable time range: 8 s to 2.048 ms, Resolution: 8 s (error: +8 s)) Count clock: fX/64 (measurable time range: 16 s to 4.096 ms, Resolution: 16 s (error: +16 s)) Count clock: fX/256 (measurable time range: 64 s to 16.384 ms, Resolution: 64 s (error: +64 s)) Remote controller carrier generator circuit output (Carrier output: 1 s to 128 s, Resolution: 1 s)
0
1
1
0
1
1
Value indicated by parentheses is for when ( ): f SYS (system clock) = fX = 4MHz TMRES 0 1 8-Bit Timer Reset Flag Data read out is always "0" Resets 8-bit counter and IRQTM
TMEN 0 1
8-Bit Timer Count Enable Flag Stops 8-bit timer count operation Enable 8-bit timer count operation (falling edge)
Notes 1. When the STOP mode is released, bit 3 must be set. 2. Bit 2 is a write-only bit. Caution If the system clock is changed while the timer is counting, an error occurs in the timer as follows (when system clock fX = 4 MHz): * High-speed mode 16/fX Normal mode 32/fX ... (Error due to resolution of set timer) +1.5 s * Normal mode 32/fX High-speed mode 16/fX ... (Error due to resolution of set timer) -1.5 s
Data Sheet U14360EJ1V0DS00
39
PD17230, 17231, 17232, 17233, 17234, 17235, 17236
NRZLTMM
7 x 6 5 4 3 2 1 0 Address Peripheral register: 03H On reset Undefined R/W R/W
7-bit modulo register
Bit 7 0 1
Output Control of REM Pin When NRZ = 1, carrier output to REM pin When NRZ = 1, high-level output to REM pin
NRZHTMM
7 0 6 5 4 3 2 1 0 Address Peripheral register: 04H On reset Undefined R/W R/W
7-bit modulo register
Bit 7 Fixed to 0
40
Data Sheet U14360EJ1V0DS00
PD17230, 17231, 17232, 17233, 17234, 17235, 17236
5.3 Carrier Generator Circuit for Remote Controller
PD17236 is provided with a carrier generator circuit for the remote controller.
The remote controller carrier generator circuit consists of a 7-bit counter, NRZ high-level timer modulo register (NRZHTMM), and NRZ low-level timer modulo register (NRZLTMM). The high-level and low-level periods are set in the corresponding modulo registers through the DBF to determine the carrier duty factor and carrier frequency. Either the system clock (fX) divided by two or the original oscillation can be selected by mask option as an input to the 7-bit counter (where the clock for generating carrier is RfX). When RfX is oscillated by a 4-MHz oscillator, therefore, the input clock is 2 MHz (fX/2) or 4 MHz (fX). The NRZ high-level output timer modulo register is called NRZHTMM, and the NRZ low-level timer modulo register is called NRZLTMM. Data is written to these registers by the PUT instruction. The contents for these register are read by the GET instruction. Bit 7 of NRZLTMM specifies whether the carrier or high level is output to the REM pin. To output the carrier, be sure to clear bit 7 to 0. 5.3.1 Remote controller signal output control
The REM pin, which outputs the carrier, is controlled by bits NRZ and NRZBF for the register file and timer 0. While the NRZ content is "1", the clock generated by the remote controller carrier generator circuit is output to the REM pin; while the NRZ content is "0", the REM pin outputs a low level. The NRZBF content is automatically transferred to NRZ by the interrupt signal generated by timer 0. If data is set in NRZBF in advance, the REM pin status changes in synchronization with the timer 0 counting operation. If the interrupt signal is generated from timer 0 with the REM pin at the high level, NRZ being "1", and the carrier clock at the high level, the REM pin output is not in accordance with the updated content of NRZ, until the carrier clock goes low. This processing is useful for holding the high level pulse width from the output carrier constant (refer to the figure below). When the content of NRZ is "0", the remote controller carrier generator circuit stops. However, if the clock for timer 0 is output from the remote controller carrier generator circuit, the clock continues to operate, even when the NRZ content becomes "0". An actual example showing a remote controller signal output to the REM pin is presented below.
Data Sheet U14360EJ1V0DS00
41
PD17230, 17231, 17232, 17233, 17234, 17235, 17236
When bit 7 of NRZLTMM is 0 (carrier output)
NRZ
REM
MAX. 500 ns (delay)Note (fX = 4 MHz, RfX = fX/2)
REM pin does not go low until carrier goes low even if NRZ becomes 0
Note
Value when (TMCK1, TMCK0) (1, 1). When (TMCK1, TMCK0) = (1, 1), the value differs depending on how NRZ is manipulated. If NRZ is set by an instruction, the width of the first high-level pulse may be shortened. If NRZ is set by data transferred from NRZBF, the high-level pulse is delayed by the low-level pulse of the carrier clock.
When bit 7 of NRZLTMM is 0 (carrier not output)
NRZ
REM
3 0
2 0
1 0
0 NRZ
Address RF : 12H
On reset 0H
R/W R/W
NRZ 0 1
NRZ Data Outputs low level to REM pin Outputs a carrier to REM pin or high level output
3 0
2 0
1 0
0 NRZBF
Address RF : 11H
On reset 0H
R/W R/W
NRZBF 0 1
NRZ Data Output Next NRZ buffer bit. Transfered to NRZ by interrupt signal of timer 0.
42
Data Sheet U14360EJ1V0DS00
PD17230, 17231, 17232, 17233, 17234, 17235, 17236
Setting carrier frequency and duty factor Where the system clock frequency is fX, carrier frequency is fC, and carrier generation clock is RfX: * * When RfX = fX/2: When RfX = fX : (division ratio) = fX/(2 x fC) (division ratio) = fX/fC
is divided into m:n and is set in the modulo registers as follows: High-level period set value = { Low-level period set value = { Example x m/(m + n)} - 1 x n/(m + n)} - 1
Where fC = 38 kHz, duty factor (high-level period) = 1/3, fX = 4 MHz, and RfX = fX/2: = 4 MHz/(2 x 38 kHz) = 52.6 m:n = 1:2 From the above, the value of the modulo register is: High-level period . . 17 = Low-level period .= 34 . Therefore, the carrier frequency is 37.74 kHz. Table 5-1. Carrier Frequency List
(1) Where fX = 4 MHz and RfX = fX/2
Set Value NRZHTMM 00H 01H 04H 09H 0FH 0FH 11H 11H 19H 3FH 7FH NRZLTMM 00H 02H 04H 09H 10H 21H 21H 22H 35H 3FH 7FH 0.5 1.0 2.5 5.0 8.0 8.0 9.0 9.0 13.0 32.0 64.0 0.5 1.5 2.5 5.0 8.0 17.0 17.0 17.5 27.0 32.0 64.0 1.0 2.5 5.0 10.0 16.5 25.0 26.0 26.5 40.0 64.0 120.0 1000 400 200 100 60.6 40.0 38.5 37.7 25.0 15.6 7.8 1/2 2/5 1/2 1/2 1/2 1/3 1/3 1/3 1/3 1/2 1/2 tH (s) tL (s) 1/fC (s) fC (kHz) Duty
Data Sheet U14360EJ1V0DS00
43
PD17230, 17231, 17232, 17233, 17234, 17235, 17236
(2) Where fX = 4 MHz, RfX = fX (original oscillation)
Set Value NRZHTMM 00H 01H 04H 09H 0FH 0FH 11H 11H 19H 3FH 7FH NRZLTMM 00H 02H 04H 09H 10H 21H 21H 22H 35H 3FH 7FH 0.25 0.5 1.25 2.5 4.0 4.0 4.5 4.5 6.5 16.0 32.0 0.25 0.75 1.25 2.5 4.25 8.5 8.5 8.75 13.5 16.0 32.0 0.5 1.25 2.5 5.0 8.25 12.5 13.0 13.25 20.0 32.0 60.0 2000 800 400 200 121 80 76.9 75.47 50 31.25 16.6 1/2 2/5 1/2 1/2 1/2 1/3 1/3 1/3 1/3 1/2 1/2 tH (s) tL (s) 1/fC (s) fC (kHz) Duty
tH
tL
REM (fC) 1/fC
44
Data Sheet U14360EJ1V0DS00
PD17230, 17231, 17232, 17233, 17234, 17235, 17236
5.3.2 Countermeasures against noise during transmission (carrier output)
When a signal is transmitted from the transmitter of a remote controller, a peak current of 0.5 to 1 A may flow through the infrared LED. Since two batteries are usually used as the power source of the transmitter, several of equivalent resistance (r) exists in the power source as shown in Figure 5-2. This resistance increases to 10 to 20 if the supply voltage drops to 2 V. While the carrier is output from the REM pin (while the infrared LED lights), therefore, a highfrequency noise may be generated on the power lines due to the voltage fluctuation that may take place especially during switching. To minimize the influence on the microcontroller of this high-frequency noise, take the following measures: <1> Separate the power lines of the microcontroller from the power lines of the infrared LED with the terminals of the batteries at the center. Use thick power lines and keep the wiring short. <2> Locate the resonator as close as possible to the microcontroller and shield it with GND lines (as indicated by the shaded portion in the figure below). <3> Locate the capacitor for stabilization of the power supply closely to the power lines of the microcontroller. Also, use a capacitor to eliminate high-frequency noise. <4> To prevent data from changing, do not execute an interrupt that requires read/write processing and stack, such as key scan interrupt, and the CALL/RET instruction, while the carrier is output. <5> To improve the reliability in case of program hang-up, use the watchdog timer. Figure 5-2. Example of Countermeasures against Noise
0.5 to 1 A Infrared LED
REM
VDD Microcomputer r + - Batteries VSS
Data Sheet U14360EJ1V0DS00
45
PD17230, 17231, 17232, 17233, 17234, 17235, 17236
6. BASIC INTERVAL TIMER/WATCHDOG TIMER
The basic interval timer has a function to generate the interval timer interrupt signal and watchdog timer reset signal.
6.1
Source Clock for Basic Interval Timer
The system clock (fX) is divided, to generate the source clock for the basic interval timer. The input clock frequency for the basic interval timer is fX/27. When the CPU is set in the STOP mode, the basic interval timer also stops.
6.2
Controlling Basic Interval Timer
The basic interval timer is controlled by the bits on the register file. That is, the basic interval timer is reset by BTMRES. The frequency for the interrupt signal, output by the basic interval timer, is selected by BTMMD, and the watchdog timer is reset by WDTRES. Figure 6-1. Basic Interval Timer Configuration
fX /2 18 fX /2 20
System clock fX
1/2 7 divider
1/2 11 divider
1/2 divider
1/2 divider
1/2 divider
Selector B
Reset signal output
BTMRES
WDTRES
BTMCK
IRQBTM
46
Data Sheet U14360EJ1V0DS00
PD17230, 17231, 17232, 17233, 17234, 17235, 17236
3 WDTRES
2 BTMCK
1 BTMRES
0 0
Address RF : 03H
On reset 0H
R/W R/WNote
BTMRES 0 1
Basic Interval Timer Reset Data read out is always "0" Writing "1" resets basic interval timer
BTMCK 0 1
Basic Interval Timer Mode Selection Generates interrupt signal IRQBTM every fX/220 Generates interrupt signal IRQBTM every fX/218
WDTRES 0 1
Watchdog Timer Reset Data read out is always "0" Writing "1" resets watchdog timer (fX/221 counter)
Note
Bits 1 and 3 are write-only bits.
Data Sheet U14360EJ1V0DS00
47
PD17230, 17231, 17232, 17233, 17234, 17235, 17236
6.3 Operation Timing for Watchdog Timer
The basic interval timer can be used as a watchdog timer. Unless the watchdog timer is reset within a fixed timeNote, it judges that "the program has hung up", and the
PD17236 is reset. It is therefore necessary to reset through programming the watchdog timer with in a fixed time.
The watchdog timer can be reset by setting WDTRES to 1. Note Fixed time: approx. 340 ms (at 4 MHz)
Caution The watchdog timer cannot be reset in the shaded range in Figure 6-2. Therefore, set WDTRES before both the fX/221 and fX/220 signals go high. Figure 6-2. Watchdog Timer Operation Timing
fX/218 fX/219 fX/220 fX/221 INTBTM (fX/220) INTBTM (fX/218) Reset signal Watchdog timer reset signal Reset signal goes low if WDTRES is not set
WDTRES Setting WDTRES at this timing is invalid
48
Data Sheet U14360EJ1V0DS00
PD17230, 17231, 17232, 17233, 17234, 17235, 17236
7. 7.1 INTERRUPT FUNCTIONS Interrupt Sources
PD17236 is provided with three interrupt sources.
When an interrupt has been accepted, the program execution automatically branches to a predetermined address, which is called a vector address. A vector address is assigned to each interrupt source, as shown in Table 7-1. Table 7-1. Vector Address
Priority 1 2 3 8-bit timer
Interrupt Source
Ext/Int Internal External Internal
Vector Address 0003H 0002H 0001H
INT pin rising and falling edges Basic interval timer
When more than one interrupt request is issued at the same time, the interrupts are accepted in sequence, starting from the one with the highest priority. Whether an interrupt is enabled or disabled is specified by the EI or DI instruction. The basic condition under which an interrupt is accepted is that the interrupt is enabled by the EI instruction. While the DI instruction is executed, or while an interrupt is accepted, the interrupt is disabled. To enable accepting an interrupt after the interrupt has been processed, the EI instruction must be executed before the RETI instruction. Accepting the interrupt is enabled by the EI instruction after the instruction next to the EI instruction has been executed. Therefore, no interrupt can be accepted between the EI and RETI instructions. Caution In interrupt processing, only the BCD, CMP, CY, Z, IXE flags are automatically saved to the stack by the hardware, to a maximum of three levels. Also, within the interrupt processing contents, when peripheral hardware (timer, A/D converter, etc. ) is accessed, the DBF and WR contents are not saved by the hardware. Accordingly, it is recommended that at the beginning of interrupt processing DBF and WR be saved by software to RAM, and immediately before finishing interrupt processing the saved contents be returned to thier original location.
Data Sheet U14360EJ1V0DS00
49
PD17230, 17231, 17232, 17233, 17234, 17235, 17236
7.2 Hardware of Interrupt Control Circuit
This section describes the flags of the interrupt control circuit. (1) Interrupt request flag and interrupt enable flag The interrupt request flag (IRQxxx) is set to 1 when an interrupt request is generated, and is automatically cleared to 0 when the interrupt processing is excuted. An interrupt enable flag (IPxxx) is provided to each interrupt request flag. When the IPxxx flag is 1, the interrupt is enabled; when it is 0, the interrupt is disabled. (2) EI/DI instruction Whether an accepted interrupt is executed or not is specified by the EI or DI instruction. When the EI instruction is executed, INTE (interrupt enable flag), which enables the interrupt, is set to 1. The INTE flag is not registered on the register file. Consequently, the status of this flag cannot be checked by an instruction. The DI flag clears the INTE flag to 0 to disable all the interrupts. The INTE flag is also cleared to 0 at reset, disabling all the interrupts. Table 7-2. Interrupt Request Flags and Interrupt Enable Flag
Interrupt Request Flag IRQTM IRQ IRQBTM Interrupt Enable Flag IPTM IP IPBTM
Signal Setting Interrupt Request Flag Reset by 8-bit timer. Set when edge of INT pin input signal is detected Reset by basic interval timer.
7.2.1
INT
This flag reads the INT pin status. When a high level is input to the INT pin, this flag is set to "1"; when a low level is input, the flag is reset to "0".
3 0 2 0 1 0 0 INT Address RF : 0FH On reset Undefined R/W R
INT 0 1
INT Pin Level Detection INT pin : Low level INT pin : High level
50
Data Sheet U14360EJ1V0DS00
PD17230, 17231, 17232, 17233, 17234, 17235, 17236
7.2.2 IEG
This pin selects the interrupt edge to be detected on the INT pin. When this flag is "0", the interrupt is detected at the rising edge; when it is "1", the interrupt is detected at the falling edge.
3 0 2 0 1 0 0 IEG Address RF : 1FH On reset 0H R/W R/W
IEG 0 1
INT Pin Interrupt Detection Edge Selection Rising edge of INT pin Falling edge of INT pin
7.2.3
Interrupt enable flag
This flag enables each interrupt source. When this flag is "1", the corresponding interrupt is enabled; when it is "0", the interrupt is disabled.
3 0 2 IPBTM 1 IP 0 IPTM Address RF : 2FH On reset 0H R/W R/W
IPTM 0 1
8-Bit Timer Interrupt Enable Flag Disables interrupt acceptance by 8-bit timer Enables interrupt acceptance by 8-bit timer
IP 0 1
INT Pin Interrupt Enable Flag Disables interrupt acceptance by INT pin input Enables interrupt acceptance by INT pin input
IPBTM 0 1
Basic Interval Timer Interrupt Enable Flag Disables interrupt acceptance by basic interval timer Enables interrupt acceptance by basic interval timer
Data Sheet U14360EJ1V0DS00
51
PD17230, 17231, 17232, 17233, 17234, 17235, 17236
7.2.4 IRQ
This is an interrupt request flag that indicates the interrupt request status. When an interrupt request is generated, this flag is set to "1". When the interrupt has been accepted, the interrupt request flag is reset to "0". The interrupt request flag can be read or written by the program. Therefore, when it is set to "1", an interrupt can be generated by the software. By writing "0" to the flag, the interrupt pending status can be canceled.
3 0 2 0 1 0 0 IRQBTM Address RF : 3DH On reset 0H R/W R/W
IRQBTM 0 1
Basic Interval Timer Interrupt Request Flag Interrupt request has not been made. Basic interval timer interrupt request has been made.
3 0
2 0
1 0
0 IRQ
Address RF : 3EH
On reset 0H
R/W R/W
IRQ 0 1
INT Pin Interrupt Request Flag Interrupt request has not been made. Interrupt request has been made at rising edge or falling edge of INT input.
3 0
2 0
1 0
0 IRQTM
Address RF : 3FH
On reset 1H
Note
R/W R/W
IRQTM 0 1
8-Bit Timer Interrupt Request Flag Interrupt request has not been made. 8-bit timer interrupt request has been made.
Note
It is also set to 1H after releasing the STOP mode.
52
Data Sheet U14360EJ1V0DS00
PD17230, 17231, 17232, 17233, 17234, 17235, 17236
7.3 Interrupt Sequence
If IRQxx flag is set to "1" when IPxx flag is "1", interrupt processing is started after the instruction cycle of the instruction executed when IRQxx flag was set has ended. Since the MOVT instruction, EI instruction, and the instruction which matches the condition to skip use two instruction cycles, the interrupt enabled while this instruction is executed is processed after the second instruction cycle is over. If IPxx flag is "0", the interrupt processing is not performed even if IRQxx flag is set, until IPxx flag is set. If two or more interrupts are enabled simultaneously, the interrupts are processed starting from the one with the highest priority. The interrupt with the lower priority is kept pending until the processing of the interrupt with the higher priority is finished. 7.3.1 Operations when interrupt is accepted
When an interrupt has been accepted, the CPU performs processing in the following sequence:
Clears IRQxxx corresponding to INTE flag and accepted interrupt
Decrements value of stack pointer by 1 (SP - 1)
Saves contents of program counter to stack addressed by stack pointer
Loads vector address to program counter
Save contents of PSWORD to interrupt stack register
One instruction cycle is required to perform the above processing.
Data Sheet U14360EJ1V0DS00
53
PD17230, 17231, 17232, 17233, 17234, 17235, 17236
7.3.2 Returning from interrupt processing routine
To return from an interrupt processing routine, use the RETI instruction. Then the following processing is executed within an instruction cycle.
Loads contents of stack addressed by stack pointer to program counter
Loads contents of interrupt stack register to PSWORD
Increments value of stack pointer by 1
To enable an interrupt after the processing of an interrupt has been finished, the EI instruction must be executed immediately before the RETI instruction. Accepting the interrupt is enabled by the EI instruction after the instruction next to the EI instruction has been executed. Therefore, the interrupt is not accepted between the EI and RETI instructions.
54
Data Sheet U14360EJ1V0DS00
PD17230, 17231, 17232, 17233, 17234, 17235, 17236
8. STANDBY FUNCTIONS
PD17236 is provided with HALT and STOP modes as standby functions.
By using the standby function, current consumption can be reduced. In the HALT mode, the program is not executed, but the system clock fX is not stopped. This mode is maintained, until the HALT mode release condition is satisfied. In the STOP mode, the system clock is stopped and program execution is stopped. This mode is maintained, until the STOP mode release condition is satisfied. The HALT mode is set, when the HALT instruction has been executed. The STOP mode is set, when the STOP instruction has been executed.
8.1
HALT Mode
In this mode, program execution is temporarily stopped, with the main clock continuing oscillating, to reduce current consumption. Use the HALT instruction to set the HALT mode. The HALT mode releasing condition can be specified by the operand for the HALT instruction, as shown in Table 8-1. After the HALT mode has been released, the operation is performed as shown in Table 8-2 and Figure 8-1. Caution Do not execute an instruction that clears the interrupt request flag (IRQxxx) for which the interrupt enable flag (IPxxx) is set immediately before the HALT 8H instruction; otherwise, the HALT mode may not be set. Table 8-1. HALT Mode Releasing Conditions
Operand Value 0010B (02H) Releasing Conditions When interrupt request (IRQTM) occurs for 8-bit timer <1> When interrupt request (IRQTM, IRQBTM, or IRQ), whose interrupt enable flag (IPTM, IPBTM, or IP) is set, occurs <2> When any of P0A0-P0A3 pins goes low <3> When P0B0-P0B3, P0C0-P0C3, and P0D0-P0D3 are used as input pins and any of these goes low Setting prohibited
1000B (08H)
Other than above
Table 8-2. Operations After HALT Mode Release (1/2) (a) HALT 08H
HALT Mode Released by: Low-level input of P0A0-P0A3, P0B0-P0B3, P0C0-P0C3, P0D0-P0D3 When release condition is satisfied by interrupt EI Interrupt Status Don't care Interrupt Enable Flag Don't care Operations after HALT Mode Release Instruction next to HALT is executed
DI
Disabled Enabled Disabled Enabled
Standby mode is not released Instruction next to HALT is executed Standby mode is not released Branches to interrupt vector address
Data Sheet U14360EJ1V0DS00
55
PD17230, 17231, 17232, 17233, 17234, 17235, 17236
Table 8-2. Operations After HALT Mode Release (2/2) (b) HALT 02H
HALT Mode Released by: 8-bit timer Interrupt Status DI Interrupt Enable Flag Disabled Enabled EI Disabled Enabled Branches to interrupt vector address Operations after HALT Mode Release Instructions are executed from the instruction next to the HALT instruction.
8.2
HALT Instruction Execution Conditions
The HALT instruction can be executed, only under special conditions, as shown in Table 8-3, to prevent the program from hangup. If the conditions in Table 8-3 are not satisfied, the HALT instruction is treated as an NOP instruction. Table 8-3. HALT Instruction Execution Conditions
Operand Value 0010B (02H) 1000B (08H) Execution Conditions When all interrupt request flags (IRQTM) of 8-bit timer are reset <1> When interrupt request flag (IRQTH, IRQBTM, or IRQ) is reset, corresponding to interrupt whose interrupt enable flag (IPTM, IPBTM, or IP) is set <2> When high level is input to all P0A0-P0A3 pins <3> When P0B0-P0B3, P0C0-P0C3, and P0D0-P0D3 are used as input pins and any of these goes high Setting prohibited
Other than above
56
Data Sheet U14360EJ1V0DS00
PD17230, 17231, 17232, 17233, 17234, 17235, 17236
8.3 STOP Mode
In the STOP mode, the system clock (fX) oscillation is stopped and the program execution is stopped to minimize current consumption. To set the STOP mode, use the STOP instruction. The STOP mode releasing condition can be specified by the STOP instruction operand, as shown in Table 8-4. After the STOP mode has released, the operation is performed as follows: <1> Resets IRQTM. <2> Starts the basic interval timer and watchdog timer (does not reset). <3> Resets and starts the 8-bit timer. <4> Executes the instruction next to [STOP 8H] when the current value of the 8-bit counter coincides with the value of the modulo register (IRQTM is set). The PD17236 oscillator is stopped, when the STOP instruction has been executed (i.e., in the STOP mode). Oscillation is not resumed, until the STOP mode is released. After the STOP mode has been released, the HALT mode is set. Set the time required to release the HALT mode by using the timer with modulo function. The time that elapses, after the STOP mode has been released by occurrence of an interrupt, until an operation mode is set, is shown in the following table. Caution Do not execute an instruction that clears the interrupt request flag (IRQxxx) for which the interrupt enable flag (IPxxx) is set immediately before the STOP 8H instruction; otherwise, the STOP mode may not be set.
8-Bit Modulo Register Set Value (TMM) Time Required to Set Operation Mode after STOP Mode Release At 4 MHz 40H FFH 4.160 ms (64 s x 65) 16.384 ms (64 s x 256)
Caution To set the time required for an operation mode to be set after the STOP mode has been released, make sure that sufficient time is allowed for oscillation to stabilize. Remark Set the 8-bit modulo timer before executing STOP instruction. Table 8-4. STOP Mode Releasing Conditions
Operand Value 1000B (08H) Releasing Conditions <1> When any of P0A0-P0A3 pins goes low <2> When P0B0-P0B3, P0C0-P0C3, and P0D0-P0D3 are used as input pins and any of these goes low <3> If the interrupt request (IRQ) of an interrupt for which the INT pin interrupt enable flag (IP) is set is generated at the rising or falling edge of the INT pin Setting prohibited
Other than above
Data Sheet U14360EJ1V0DS00
57
PD17230, 17231, 17232, 17233, 17234, 17235, 17236
8.4 STOP Instruction Execution Conditions
The STOP instruction can be executed, only under special conditions, as shown in Table 8-5, to prevent the program from hang-up. If the conditions in Table 8-5 are not satisfied, the STOP instruction is treated as an NOP instruction. Table 8-5. STOP Instruction Execution Conditions
Operand Value 1000B (08H) Execution Conditions <1> High level input for all P0A0-P0A3 pins <2> When P0B0-P0B3, P0C0-P0C3, and P0D0-P0D3 are used as input pins and all pins are high <3> If the INT pin interrupt request flag (IRQ) for an interrupt for which the INT pin interrupt enable flag (IP) is set is reset Setting prohibited
Other than above
8.5
Releasing Standby Mode
Operations for releasing the STOP and HALT modes will be as shown in Figure 8-1. Figure 8-1. Operations After Standby Mode Release (a) Releasing STOP mode by interrupt
Wait (time set by TMM)
STOP instruction Stanby release signal Operation mode Oscillation
STOP mode Oscillation stops
HALT mode Oscillation
Operation mode
Clock
(b) Releasing HALT mode by interrupt
HALT instruction
Stanby release signal Operation mode HALT mode Operation mode
Clock
Oscillation
Remark The dotted line indicates the operation to be performed when the interrupt request, releasing the standby mode, has been accepted.
58
Data Sheet U14360EJ1V0DS00
PD17230, 17231, 17232, 17233, 17234, 17235, 17236
9. 9.1 RESET Reset by Reset Signal Input
When a low-level signal more than 10 s is input to the RESET pin, PD17236 is reset. When the system is reset, the oscillator circuit remains in the HALT mode and then enters an operation mode, like when the STOP mode has been released. The wait time, after the reset signal has been removed, is 16.384 ms (fX = 4 MHz). On power application, input the reset signal at least once because the internal circuitry operations are not stable. When PD17225 is reset, the following initialization takes place: (1) Program counter is reset to 0. (2) Flags in the register file are initialized to their default values (for the default values, refer to Figure 11-1 Register Files). (3) The default value (0320H) is written to the data buffer (DBF). (4) The hardware peripherals are initialized. (5) The system clock (fX) stops oscillation. When the RESET pin is made high, the system clock starts oscillating, and the program execution starts from address 0 about 16 ms (at 4 MHz) later. Figure 9-1. Reset Operation by RESET Input
Wait (about 16 ms at 4 MHz) RESET Operation mode or standby mode Starts from address 0H
HALT mode
Operation mode
Oscillation stops
9.2
Reset by Watchdog Timer (With RESET pin internally pulled down)
When the watchdog timer operates during program execution, the RESET pin is internally pulled down, and the program counter is reset to 0 (normally, the RESET pin is pulled up). If the watchdog timer is not reset for a fixed period of time, the program can be restarted from address 0H. Program so that the watchdog timer is reset at intervals of within 340 ms (at fX = 4 MHz) (set the WDTRES flag).
Data Sheet U14360EJ1V0DS00
59
PD17230, 17231, 17232, 17233, 17234, 17235, 17236
9.3 Reset by Stack Pointer (With RESET pin internally pulled down)
When the value of the stack pointer reaches 6H or 7H during program execution, the RESET pin is internally pulled down, and the program counter is reset to 0 (normally, the RESET pin is pulled up). Therefore, if an interrupt or CALL instruction is executed when the value of the stack pointer is 0 (stack underflow) or if the stack level exceeds 6 as a result of execution of the RET instruction because the correspondence between the CALL and RET instructions is not established (stack overflow), the program can be restarted from address 0H. Table 9-1. Status of Each Hardware After Reset
RESET Input During Standby Mode 0000H Input/output Output latch Data memory (RAM) General-purpose data memory (Except DBF, port register) DBF System register (SYSREG) WR Input 0 Retains previous status 0320H 0 Retains previous status RESET Input During Operation 0000H Input 0 Undefined
Hardware Program counter (PC) Port
0320H 0 Undefined
Control register 8-bit timer Counter (TMC) Modulo register (TMM) Remote controller carrier generator
Refer to Figure 11-1 Register Files 00H FFH 00H FFH Undefined
NRZ high-level timer modulo register (NRZHTMM) Retains previous NRZ low-level timer modulo register (NRZLTMM) status 00H
Basic interval timer/watchdog timer counter
00H
60
Data Sheet U14360EJ1V0DS00
PD17230, 17231, 17232, 17233, 17234, 17235, 17236
10. LOW-VOLTAGE DETECTOR CIRCUIT (WITH RESET PIN INTERNALLY PULLED DOWN)
The RESET pin is internally pulled down for initialization (reset) to prevent program hang-up that may take place when the batteries are replaced, if the circuit detects a low voltage. A drop in the supply voltage is detected if the status of VDD = 1.7 to 2.0 V lasts for 1 ms or longer. Note, however, that 1 ms is the guaranteed value and that the microcontroller may be reset even if the above low-voltage condition lasts for less than 1 ms. Although the voltage at which the the reset function is effected ranges from 1.7 to 2.0 V, the program counter is prevented from hang-up even if the supply voltage drops until the reset function is effected, if the instruction execution time is from 4 to 32 s. Note that some oscillators stop oscillating before the reset function is effected. The low-voltage detector circuit can be set arbitrarily by the mask option.
Data Sheet U14360EJ1V0DS00
61
PD17230, 17231, 17232, 17233, 17234, 17235, 17236
11. ASSEMBLER RESERVED WORDS 11.1 Mask Option Directives
When developing the PD17236 program, mask options must be specified by using mask option directives in the program. To select the PIA0 pin and remote controller carrier generator clock of the PD17236, a mask option must be specified. 11.1.1 OPTION and ENDOP directives
That portion of the program enclosed by the OPTION and ENDOP directives is called a mask option definition block. This block is described in the following format: Description format: Symbol [Label: ] Mnemonic OPTION : : : ENDOP Operand Comment [;Comment]
11.1.2
Mask option definition directives
Table 11-1 lists the directives that can be used in the mask option definition block. Here is an example of mask option definition: Description example: Symbol Mnemonic OPTION OPTP1A0 OPTPOC OPTRFX INP1A0 USEPOC USEFX ; Sets P1A0 pin in input mode ; Internal low-voltage detector circuit ; Sets clock for carrier generation of remote controller ; carrier generator to fX ENDOP Operand Comment
62
Data Sheet U14360EJ1V0DS00
PD17230, 17231, 17232, 17233, 17234, 17235, 17236
Table 11-1. Mask Option Definition Directives
Name P1A0 Directive OPTP1A0 Operands 1 1st Operand INP1A0 (Sets P1A0 pin in input mode) OUTP1A0 (Sets P1A0 pin in output mode) RFX OPTRFX 1 USEFX (Sets clock for carrier generation to fX) USEHALFX (Sets clock for carrier generation to fX/2) POC OPTPOC 1 USEPOC (low-voltage detector circuit provided) NOUSEPOC (low-voltage detector circuit not provided) 2nd Operand 3rd Operand 4th Operand
11.2 Reserved Symbols
The symbols defined by the PD17236 device file are listed in Table 11-2. The defined symbols are the following register file names, port names, and peripheral hardware names. 11.2.1 Register file
The names of the symbols assigned to the register file are defined. These registers are accessed by the PEEK and POKE instructions through the window register (WR). Figure 11-1 shows the register file. 11.2.2 Registers and ports on data memory
The names of the registers assigned at addresses 00H through 7FH on the data memory and the names of ports assigned to address 70H and those that follow, and system register names are defined. Figure 11-2 shows the data memory configuration. 11.2.3 Peripheral hardware
The names of peripheral hardware accessed by the GET and PUT instructions are defined. Table 11-3 shows the peripheral hardware.
Data Sheet U14360EJ1V0DS00
63
PD17230, 17231, 17232, 17233, 17234, 17235, 17236
Table 11-2. Reserved Symbols (1/3)
Symbol Name DBF3 DBF2 DBF1 DBF0 AR3 AR2 AR1 AR0 WR BANK IXH MPH MPE IXM MPL IXL RPH RPL PSW BCD CMP CY Z IXE P0A0 P0A1 P0A2 P0A3 P0B0 P0B1 P0B2 P0B3 P0C0 P0C1 P0C2 P0C3 P0D0 P0D1 P0D2 P0D3 Attribute MEM MEM MEM MEM MEM MEM MEM MEM MEM MEM MEM MEM FLG MEM MEM MEM MEM MEM MEM FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG Value 0.0CH 0.0DH 0.0EH 0.0FH 0.74H 0.75H 0.76H 0.77H 0.78H 0.79H 0.7AH 0.7AH 0.7AH.3 0.7BH 0.7BH 0.7CH 0.7DH 0.7EH 0.7FH 0.7EH.0 0.7FH.3 0.7FH.2 0.7FH.1 0.7FH.0 0.70H.0 0.70H.1 0.70H.2 0.70H.3 0.71H.0 0.71H.1 0.71H.2 0.71H.3 0.72H.0 0.72H.1 0.72H.2 0.72H.3 0.73H.0 0.73H.1 0.73H.2 0.73H.3 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Bits 15-12 of data buffer Bits 11-8 of data buffer Bits 7-4 of data buffer Bits 3-0 of data buffer Bits 15-12 of address register Bits 11-8 of address register Bits 7-4 of address register Bits 3-0 of address register Window register Bank register Index register, high Data memory row address pointer, high Memory pointer enable flag Index register, middle Data memory row address pointer, low Index register, low General register pointer, high General register pointer, low Program status word BCD flag Compare flag Carry flag Zero flag Index enable flag Bit 0 of port 0A Bit 1 of port 0A Bit 2 of port 0A Bit 3 of port 0A Bit 0 of port 0B Bit 1 of port 0B Bit 2 of port 0B Bit 3 of port 0B Bit 0 of port 0C Bit 1 of port 0C Bit 2 of port 0C Bit 3 of port 0C Bit 0 of port 0D Bit 1 of port 0D Bit 2 of port 0D Bit 3 of port 0D
64
Data Sheet U14360EJ1V0DS00
PD17230, 17231, 17232, 17233, 17234, 17235, 17236
Table 11-2. Reserved Symbols (2/3)
Symbol Name P0E0 P0E1 P0E2 P0E3 P1A0 SP SYSCK WDTRES BTMCK BTMRES INT NRZBF NRZ P0EBPU0 P0EBPU1 P0EBPU2 P0EBPU3 IEG P0BBIO0 P0BBIO1 P0BBIO2 P0BBIO3 P0EBIO0 P0EBIO1 P0EBIO2 P0EBIO3 IPBTM IP IPTM TMEN TMRES TMCK1 TMCK0 P0CGIO P0DGIO IRQBTM IRQ IRQTM TMC TMM Attribute FLG FLG FLG FLG FLG MEM FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG DAT DAT Value 0.6FH.0 0.6FH.1 0.6FH.2 0.6FH.3 1.70H.0 0.81H 0.82H.0 0.83H.3 0.83H.2 0.83H.1 0.8FH.0 0.91H.0 0.92H.0 0.97H.0 0.97H.1 0.97H.2 0.97H.3 0.9FH.0 00A6H.0 00A6H.1 00A6H.2 00A6H.3 0.0A7H.0 0.0A7H.1 0.0A7H.2 0.0A7H.3 0.0AFH.2 0.0AFH.1 0.0AFH.0 0.0B3H.3 0.0B3H.2 0.0B3H.1 0.0B3H.0 00B7H.2 00B7H.3 0.0BDH.0 0.0BEH.0 0.0BFH.0 05H 06H R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R W Bit 0 of port 0E Bit 1 of port 0E Bit 2 of port 0E Bit 3 of port 0E Bit 0 of port 1A (Input or output set by mask option) Stack pointer System clock select flag Watchdog timer reset flag Basic interval timer mode select flag Basic interval timer mode reset flag INT pin status flag NRZ buffer data flag NRZ data flag P0E0 pull-up setting flag P0E1 pull-up setting flag P0E2 pull-up setting flag P0E3 pull-up setting flag INT pin interrupt edge flag P0B0 I/O select flag P0B1 I/O select flag P0B2 I/O select flag P0B3 I/O select flag P0E0 I/O setting flag P0E1 I/O setting flag P0E2 I/O setting flag P0E3 I/O setting flag Basic interval timer interrupt enable flag INT pin interrupt enable flag Timer interrupt enable flag Timer enable flag Timer reset flag Timer clock flag Timer clock flag P0C3-P0C0 I/O select flag P0D3-P0D0 I/O select flag Basic interval timer interrupt request flag INT pin interrupt request flag Timer interrupt request flag Timer count register Timer modulo register Description
Data Sheet U14360EJ1V0DS00
65
PD17230, 17231, 17232, 17233, 17234, 17235, 17236
Table 11-2. Reserved Symbols (3/3)
Symbol Name NRZLTMM NRZHTMM AR DBF IX Attribute DAT DAT DAT DAT DAT Value 03H 04H 40H 0FH 01H R/W R/W R/W R/W -- -- Description NRZ low-level timer modulo register NRZ high-level timer modulo register Address register Fixed operand value for PUT, GET, MOVT instruction Fixed operand value for INC instruction
66
Data Sheet U14360EJ1V0DS00
PD17230, 17231, 17232, 17233, 17234, 17235, 17236
[MEMO]
Data Sheet U14360EJ1V0DS00
67
PD17230, 17231, 17232, 17233, 17234, 17235, 17236
Figure 11-1. Register Files (1/2)
Column Address Row Address Bit 3 0 Bit 2 Bit 1 Bit 0 Bit 3 1 Bit 2 Bit 1 Bit 0 Bit 3 2 Bit 2 Bit 1 Bit 0 Bit 3 3 Bit 2 Bit 1 Bit 0 TMEN 1 TMRES 0 TMCK1 0 TMCK0 0 0 0 0 SP
0
Note
1
Note
2
Note
3
Note
4
Note
5
Note
6
Note
7
Note
0 1 0
0 0 0
0 WDTRES 0 0 BTMCK 0 0 BTMRES 0 0 0
P0EBPU3 0 P0EBPU2 0 P0EBPU1 0 P0EBPU0 0 P0BBIO3 0 P0EBIO3 0 P0BBIO2 0 P0EBIO2 0 P0BBIO1 0 P0EBIO1 0 P0BBIO0 0 P0EBIO0 0 P0DGIO 1 P0CGIO 1 0 0
1 SYSCK 0 0 0 0 0 0 0 NRZ 0 0 0 0
NRZBF 0
0 0
Note On reset
Figure 11-2. Data Memory Configuration
Column address 7 8 9
0 0 1
1
2
3
4
5
6
A
B
C
D
E
F DBF
DBF3DBF2DBF1DBF0
Row address
2 3 4 5 6 7 P0E0-P0E3
AR3 AR2 AR1 AR0 WR BANK IXH IXM IXL RPH RPL PSW System register P0D0-P0D3 P0C0-P0C3 P0B0-P0B3 P1A0 P0A0-P0A3
68
Data Sheet U14360EJ1V0DS00
PD17230, 17231, 17232, 17233, 17234, 17235, 17236
Figure 11-1. Register Files (2/2)
Column Address Row Address Bit 3 0 Bit 2 Bit 1 Bit 0 Bit 3 1 Bit 2 Bit 1 Bit 0 Bit 3 2 Bit 2 Bit 1 Bit 0 Bit 3 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 0 IRQ 0 0 0
8
Note
9
Note
A
Note
B
Note
C
Note
D
Note
E
Note
F
Note
0 0 0 INT 0 0 0 IEG 0
0 0 0 P 0 0 0 0 0
IPBTM 0 IP IPTM 0 0 0 0 0 0 0 0
IRQBTM 0
0 IRQTM 1
Note
On reset P: When INT pin is high level, 1 or when INT pin is low level, 0. Table 11-3. Peripheral Hardware
Name TMC TMM NRZLTMM NRZHTMM AR
Address 05H 06H 03H 04H 40H
Valid Bit 8 8 8 8 16 Timer count register Timer modulo register
Description
Low-level timer modulo register for NRZ High-level timer modulo register for NRZ Address register
Data Sheet U14360EJ1V0DS00
69
PD17230, 17231, 17232, 17233, 17234, 17235, 17236
12. INSTRUCTION SET 12.1 Instruction Set Outline
b15 b14-b11 BIN. 0000 0001 0010 0011 0100 0101 0110 HEX. 0 1 2 3 4 5 6 ADD SUB ADDC SUBC AND XOR OR INC INC MOVT BR CALL RET SYSCAL RETSK EI DI RETI PUSH POP GET PUT PEEK POKE RORC STOP HALT NOP LD SKE MOV SKNE BR BR BR BR r, m r, m r, m r, m r, m r, m r, m AR IX DBF, @AR @AR @AR entryNote ADD SUB ADDC SUBC AND XOR OR m, #n4 m, #n4 m, #n4 m, #n4 m, #n4 m, #n4 m, #n4 0 1
0111
7
AR AR DBF, p p, DBF WR, rf rf, WR r s h
1000 1001 1010 1011 1100 1101 1110 1111
8 9 A B C D E F
r, m m, #n4 @r, m m, #n4 addr (Page 0) addr (Page 1) addr (Page 2) addr (Page 3)
ST SKGE MOV SKLT CALL MOV SKT SKF
m, r m, #n4 m, @r m, #n4 addr m, #n4 m, #n m, #n
Note
PD17234, 17235, 17236 only
70
Data Sheet U14360EJ1V0DS00
PD17230, 17231, 17232, 17233, 17234, 17235, 17236
12.2 Legend
AR ASR addr BANK CMP CY DBF entry h INTEF INTR INTSK IX MP MPE m mR mC n n4 : PAGE PC p pH pL r rf rfR rfC SP s WR (x) : Address register : Address stack register specified by stack pointer : Program memory address (low-order 11 bits) : Bank register : Compare register : Carry flag : Data buffer : Entry address of system segment : Halt releasing condition : Interrupt enable flag : Register automatically saved to stack in case of interrupt : Interrupt stack register : Index register : Data memory row address pointer : Memory pointer enable flag : Data memory address specified by mR, mC : Data memory row address (high) : Data memory column address (low) : Bit position (4 bits) Immediate data (4 bits) : Page (bit 11 and 12 of program counter) : Program counter : Peripheral address : Peripheral address (high-order 3 bits) : Peripheral address (low-order 4 bits) : General register column address : Register file address : Register file row address (high-order 3 bits) : Register file column address (low-order 4 bits) : Stack pointer : Stop releasing condition : Window register : Contents addressed by x
Data Sheet U14360EJ1V0DS00
71
PD17230, 17231, 17232, 17233, 17234, 17235, 17236
12.3 List of Instruction Sets
Instruction Code OP Code ADD r, m m, #n4 Add ADDC r, m m, #n4 INC AR IX SUB Subtract SUBC r, m m, #n4 r, m m, #n4 OR r, m m, #n4 Logical AND r, m m, #n4 XOR SKT SKF SKE Compare SKNE SKGE SKLT r, m m, #n4 Judge m, #n m, #n m, #n4 m, #n4 m, #n4 m, #n4 (r) (r) + (m) (m) (m) + n4 (r) (r) + (m) + CY (m) (m) + n4 + CY AR AR + 1 IX IX + 1 (r) (r) - (m) (m) (m) - n4 (r) (r) - (m) - CY (m) (m) - n4 - CY 00000 10000 00010 10010 00111 00111 00001 10001 00011 10011 00110 10110 00100 10100 00101 10101 11110 11111 01001 01011 11001 11011 mR mR mR mR 000 000 mR mR mR mR mR mR mR mR mR mR mR mR mR mR mR mR Operand mC mC mC mC 1001 1000 mC mC mC mC mC mC mC mC mC mC mC mC mC mC mC mC r n4 r n4 0000 0000 r n4 r n4 r n4 r n4 r n4 n n n4 n4 n4 n4
Group
Mnemonic
Operand
Operation
(m) (m) (m) n4 (r) (r) (m) (m) (m) n4
(r) (r) (r) (r) (m) (m) (m) n4
n = n, then skip CMP 0, if (m) n = 0, then skip
CMP 0, if (m) (m) - n4, skip if zero (m) - n4, skip if not zero (m) - n4, skip if not borrow (m) - n4, skip if borrow
CY (r)b3 (r)b2 (r)b1 (r)b0
Rotate
RORC
r
00111
000
0111
r
LD ST
r, m m, r @r, m
(r) (m) (m) (r) if MPE = 1 : (MP, (r)) (m) if MPE = 0 : (BANK, mR, (r)) (m) if MPE = 1 : (m) (MP, (r)) if MPE = 0 : (m) (BANK, mR, (r)) (m) n4 SP SP - 1, ASR PC, PC AR DBF (PC), PC ASR, SP SP + 1
01000 11000 01010
mR mR mR
mC mC mC
r r r
Transfer
MOV
m, @r
11010
mR
mC
r
m, #n4 MOVT DBF, @AR
11101 00111
mR 000
mC 0001
n4 0000
72
Data Sheet U14360EJ1V0DS00
PD17230, 17231, 17232, 17233, 17234, 17235, 17236
Instruction Code OP Code PUSH POP Transfer PEEK POKE GET PUT Branch BR AR AR WR, rf rf, WR DBF, p p, DBF addr @AR addr CALL @AR Subroutine entry SYSCALNote 2 SP SP - 1, ASR AR AR ASR, SP SP + 1 WR (rf) (rf) WR (DBF) (p) (p) (DBF) Note 1 PC AR SP SP - 1, ASR PC, PC10-0 addr, PAGE 0 SP SP - 1, ASR PC, PC AR SP SP - 1, ASR PC, SGR 1, PC12,11 0, PC10-8 entryH, PC7-4 0, PC3-0 entryL PC ASR, SP SP + 1 PC ASR, SP SP + 1 and skip PC ASR, INTR INTSK, SP SP + 1 INTEF 1 INTEF 0 s h STOP HALT No operation 00111 00111 00111 00111 00111 00111 Note 1 00111 11100 000 000 000 rfR rfR pH pH Operand 1101 1100 0011 0010 1011 1010 addr 0100 addr 0000 0000 0000 rfC rfC pL pL
Group
Mnemonic
Operand
Operation
00111
000
0101
0000
00111
entryH
0000
entryL
RET RETSK RETI Interrupt EI DI STOP Other HALT NOP
00111 00111 00111 00111 00111 00111 00111 00111
000 001 100 000 001 010 011 100
1110 1110 1110 1111 1111 1111 1111 1111
0000 0000 0000 0000 0000 s h 0000
Notes 1. The operation and operation codes "BR addr" of the PD17230, 17231, 17232, 17233, 17234, 17235, and 17236 are as follows: (a) PD17230
Operand addr Operation PC10-0 addr Op Code 01100
(b) PD17231
Operand addr Operation PC10-0 addr, Page 0 PC10-0 addr, Page 1 Op Code 01100 01101
(c) PD17232
Operand addr Operation PC10-0 addr, Page 0 PC10-0 addr, Page 1 PC10-0 addr, Page 2 Op Code 01100 01101 01110
Data Sheet U14360EJ1V0DS00
73
PD17230, 17231, 17232, 17233, 17234, 17235, 17236
(d) PD17233, 17234, 17235, 17236
Operand addr Operation PC10-0 addr, Page 0 PC10-0 addr, Page 1 PC10-0 addr, Page 2 PC10-0 addr, Page 3 Op Code 01100 01101 01110 01111
2. PD17234, 17235, and 17236 only
12.4 Assembler (RA17K) Built-In Macro Instruction
Legend flag n : FLG type symbol n < : Bit number > : Contents in <
Mnemonic Built-in macro SKTn SKFn SETn CLRn NOTn INITFLG
> can be omitted
Operand flag 1, ...flag n flag 1, ...flag n flag 1, ...flag n flag 1, ...flag n flag 1, ...flag n flag 1, ***< flag n> Operation if (flag 1) to (flag n) = all "1", then skip if (flag 1) to (flag n) = all "0", then skip (flag 1) to (flag n) 1 (flag 1) to (flag n) 0 if (flag n) = "0", then (flag n) 1 if (flag n) = "1", then (flag n) 0 if description = NOT flag n, then (flag n) 0 if description = flag n, then (flag n) 1 (BANK) n Label function-name flag 1, ... flag n Jump Label CALL sub-routine if description = NOT (or INV) flag, (flag) 0 if description = flag, (flag) 1 n 1n4 1n4 1n4 1n4 1n4 1n4 n = 0, 1 -- -- n4
BANKn Expantion instruction BRX CALLX INITFLGX
74
Data Sheet U14360EJ1V0DS00
PD17230, 17231, 17232, 17233, 17234, 17235, 17236
13. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25C)
Item Supply voltage Input voltage Output voltage High-level output current
Note
Symbol VDD VI VO IOH REM pin
Conditions
Ratings -0.3 to +3.8 -0.3 to VDD + 0.3 -0.3 to VDD + 0.3 Peak value rms value -36.0 -24.0 -7.5 -5.0 -22.5 -15.0 7.5 5.0 22.5 15.0 30.0 20.0 -40 to +85 -65 to +150
Unit V V V mA mA mA mA mA mA mA mA mA mA mA mA C C mW
1 pin (P0E pin)
Peak value rms value
Total of P0E pins
Peak value rms value
Low-level output current
Note
IOL
1 pin (P0B, P0C, P0D, P0E, P1A0, REM pins) Total of P0B, P0C, P0D, P1A0, REM pins Total of P0E pins
Peak value rms value Peak value rms value Peak value rms value
Operating temperature Storage temperature Power dissipation
TA Tstg Pd TA = 85 C
180
Note
Calculate rms value by this expression: [rms value] = [Peak value] x Duty
Caution Even if one of the parameters exceeds its absolute maximum rating even momentarily, the quality of the product may be degraded. The absolute maximum rating therefore specifies the upper or lower limit of the value at which the product can be used without physical damages. Be sure not to exceed or fall below this value when using the product.
Data Sheet U14360EJ1V0DS00
75
PD17230, 17231, 17232, 17233, 17234, 17235, 17236
Recommended Operating Ranges (TA = -40 to +85C, VDD = 2.0 to 3.6 V)
Item Supply voltage Symbol VDD1 Conditions fX = 1 MHz High-speed mode (Instruction execution time: 16 s) fX = 4 MHz Ordinary mode (Instruction execution time: 4 s) fX = 8 MHz High-speed mode (Instruction execution time: 4 s) High-speed mode (Instruction execution time: 2 s) 2.2 3.0 3.6 V MIN. 2.0 TYP. 3.0 MAX. 3.6 Unit V
VDD2
VDD3
VDD4
Oscillation frequency Operating temperature Low-voltage detector circuit (Mask option)
Note
fX TA TCY
1.0 -40 4
4.0 +25
8.0 +85 32
MHz C
s
Note
Reset if the status of VDD = 1.7 to 2.0 V lasts for 1 ms or longer. Program hang-up does not occur even if the voltage drops, until the reset function is effected. Some oscillators stop oscillating before the reset function is effected.
fX vs VDD
(MHZ) 10 9 8 7 6 5
System clock: fX (MHz) (Ordinary mode)
4 3
Operation guaranteed area
2
1
0.4 0
2 2.2
3
3.6
4
Supply voltage: VDD (V)
Remark The region indicated by the broken line in the above figure is the guaranteed operating range in the highspeed mode.
76
Data Sheet U14360EJ1V0DS00
PD17230, 17231, 17232, 17233, 17234, 17235, 17236
System Clock Oscillator Characteristics (TA = -40 to +85C, VDD = 2.0 to 3.6 V)
Resonator Ceramic resonator Recommended Constants Item Oscillation frequency (fX)Note 1 Conditions MIN. 1.0 TYP. 4.0 MAX. 8.0 Unit MHz
XIN
XOUT
Oscillation stabilization timeNote 2
After VDD reached MIN. in oscillation voltage range
4
ms
Notes 1. The oscillation frequency only indicates the oscillator characteristics. 2. The oscillation stabilization time is necessary for oscillation to be stabilized, after VDD application or STOP mode release. Caution To use a system clock oscillator circuit, perform the wiring in the area enclosed by the dotted line in the above figure as follows, to avoid adverse wiring capacitance influences: * Keep wiring length as short as possible. * Do not cross a signal line with some other signal lines. Do not route the wiring in the vicinity of lines through which a large current flows. * Always keep the oscillator circuit capacitor ground at the same potential as GND. Do not ground the capacitor to a ground pattern, through which a large current flows. * Do not extract signals from the oscillator circuit. External circuit example
XIN
XOUT R1
C1
C2
Data Sheet U14360EJ1V0DS00
77
PD17230, 17231, 17232, 17233, 17234, 17235, 17236
Recommended Oscillator Constants System Clock: Ceramic Resonator (TA = -40 to +85 C)
Manufacturer Part Number Frequency (MHz) Recommended Circuit Constants (pF) C1 TDK Corp. FCR4.0MC5 FCR6.0MC5 FCR8.0MC5 4.0 6.0 8.0 - - - C2 - - - Oscillation Voltage Range (VDD) MIN. (V) 2.0 2.2 MAX. (V) 3.6 Remark
Caution The oscillation circuit constants and oscillation voltage range indicate conditions for stable oscillation but do not guarantee accuracy of the oscillation frequency. If the application circuit requires accuracy of the oscillation frequency, it is necessary to set the oscillation frequency of the resonator in the application circuit. For this, it is necessary to directly contact the manufacturer of the resonator being used.
78
Data Sheet U14360EJ1V0DS00
PD17230, 17231, 17232, 17233, 17234, 17235, 17236
DC Characteristics (TA = -40 to +85C, VDD = 2.0 to 3.6 V)
Item High-level input voltage Symbol VIHI1 VIH2 VIH3 Low-level input voltage VIL1 VIL2 VIL3 High-level input leakage current Low-level input leakage current ILIH Conditions P1A0 (input), RESET, INT P0A, P0B, P0C, P0D P0E P1A0 (input), RESET, INT P0A, P0B, P0C, P0D P0E P0A, P0B, P0C, P0D, P0E, P1A0, RESET, INT INT P0E, RESET VIH = VDD MIN. 0.80VDD 0.70VDD 0.80VDD 0 0 0 TYP. MAX. VDD VDD VDD 0.2 VDD 0.3 VDD 0.35 VDD 3.0 Unit V V V V V V
A A A
k k k mA
ILIL1 ILIL2
VIL = 0 V VIL = 0 V w/o pull-up resistor 25 100 2.5 VOH = 1.0 V, VDD = 3 V -6 50 200 5 -13
-3.0 -3.0
Internal pull-up resistor
R1 R2 R3
P0E, RESET (pulled up) P0A, P0B, P0C, P0D RESET (pulled down) REM
100 400 10 -24
High-level output current
IOH
High-level output voltage Low-level output voltage
VOH VOL1 VOL2
P0E, REM P0B, P0C, P0D, P1A0 (output), REM P0E RESET = low level or STOP mode RESET pin pulled down, VDT = VDD
IOH = -0.5 mA VDD-0.3 IOL = 0.5 mA IOL = 1.5 mA 0 0 1.3 1.70 1.85
VDD 0.3 0.3 3.6 2.0
V V V V V
Data retention characteristics VDDDR Low-voltage detection voltage (mask option) POC detection pulse width Supply current VDT
TDT IDD1
VDD < VDT Operating mode (high-speed) VDD = 3 V 10% fX = 1 MHz fX = 4 MHz fX = 8 MHz
1 0.6 0.75 0.9 0.48 0.6 0.8 0.4 0.45 0.5 2.0 TA = 25 C 2.0 1.1 1.3 1.6 0.9 1.1 1.4 0.75 0.85 0.95 20.0 5.0
ms mA mA mA mA mA mA mA mA mA
IDD2
Operating mode (low-speed)
VDD = 3 V 10%
fX = 1 MHz fX = 4 MHz fX = 8 MHz
IDD3
HALT mode
VDD = 3 V 10%
fX = 1 MHz fX = 4 MHz fX = 8 MHz
IDD4
STOP mode
VDD = 3 V 10% built-in POC
A A
Data Sheet U14360EJ1V0DS00
79
PD17230, 17231, 17232, 17233, 17234, 17235, 17236
AC Characteristics (TA = -40 to +85C, VDD = 2.0 to 3.6 V)
Item CPU clock cycle time (Instruction execution time) INT high/low level width
Note
Symbol tCY1 tCY2 tINTH, tINTL tRSL VDD = 2.2 to 3.6 V
Conditions
MIN. 3.8 1.9 20
TYP.
MAX. 33 33
Unit
s s s s
RESET low level width
10
Note
The CPU clock cycle time (instruction execution time) is determined by the oscillation frequency of the resonator connected and SYSCK (RF: address 02H) of the register file. The figure on the right shows the CPU clock cycle time tCY vs. supply voltage VDD characteristics (refer to 4. CLOCK GENERATOR CIRCUIT).
CPU clock cycle time tcY ( s)
tCY vs VDD
40 33
10 9 8 7 6 5 4 3 3.8 Operation guaranteed area
2
1.9
1 0 1
2.2 2 3
3.6 4
Supply voltage VDD (V)
80
Data Sheet U14360EJ1V0DS00
PD17230, 17231, 17232, 17233, 17234, 17235, 17236
14. APPLICATION CIRCUIT EXAMPLE
* PD17235GT-xxx, 17236GT-xxx
P0D2 P0D3
1 2
28 27 26 25 24 23 22 21 20 19 18 17 16 15
P0D1 P0D0 P0C3 P0C2 P0C1 P0C0 P0B3 P0B2 P0B1 P0B0 P0A3 P0A2 P0A1 P0A0
INT 3 P0E0 4 P0E1 P0E2 P0E3 REM 3V VDD XOUT 4 MHz XIN 5 6 7 8 9 10 11
GND 12 RESET P1A0 13 14
Remarks 1. 2.
In the above circuit example, P1A0 is set in the output mode by mask option. The above example is for the 28-pin plastic SOP (375 mil). With the 30-pin plastic shrink SOP (300 mil), open IC1 (pin 15) and IC2 (pin 30).
Data Sheet U14360EJ1V0DS00
81
PD17230, 17231, 17232, 17233, 17234, 17235, 17236
15. PACKAGE DRAWINGS
28-PIN PLASTIC SOP (375 mil)
28 15
detail of lead end
P 1 A H G I J 14
F
S C D E M
M
B K
L N S
NOTE Each lead centerline is located within 0.12 mm of its true position (T.P.) at maximum material condition.
ITEM A B C D E F G H I J K L M N P
MILLIMETERS 17.90.17 0.78 MAX. 1.27 (T.P.) 0.42 +0.08 -0.07 0.10.1 2.60.2 2.50 10.30.3 7.20.2 1.60.2 0.17 +0.08 -0.07 0.80.2 0.12 0.15 +7 3 -3 P28GM-50-375B-4
82
Data Sheet U14360EJ1V0DS00
PD17230, 17231, 17232, 17233, 17234, 17235, 17236
30 PIN PLASTIC SSOP (300 mil)
30 16 detail of lead end F G T
P 1 A 15 E
L U
H I J
S
C D
NOTE
N M
M
S
B K
ITEM A B C D E F G H I J K L M N P T U MILLIMETERS 9.850.15 0.45 MAX. 0.65 (T.P.) 0.24 +0.08 -0.07 0.10.05 1.30.1 1.2 8.10.2 6.10.2 1.00.2 0.170.03 0.5 0.13 0.10 3 +5 -3 0.25 0.60.15 S30MC-65-5A4-1
Each lead centerline is located within 0.10 mm of its true position (T.P.) at maximum material condition.
Data Sheet U14360EJ1V0DS00
83
PD17230, 17231, 17232, 17233, 17234, 17235, 17236
16. RECOMMENDED SOLDERING CONDITIONS
For the PD17236 soldering must be performed under the following conditions. For details of recommended conditions for surface mounting, refer to information document "Semiconductor Device Mounting Technology Manual" (C10535E). For other soldering methods, please consult with NEC personnel. Table 16-1. Soldering Conditions of Surface Mount Type (1) PD17235GT-xxx: 28-pin plastic SOP (375 mil) PD17236GT-xxx: 28-pin plastic SOP (375 mil)
Soldering Method Infrated reflow VPS Wave soldering Partial heating Soldering Conditions Package peak temperature: 235 C, Time: 30 seconds max. (210 C min.), Number of times: 2 max. Package peak temperature: 215 C, Time: 40 seconds max. (200 C min.), Number of times: 2 max. Solder bath temperature: 260 C max, Time: 10 seconds max., Number of times: once, preheating temperature: 120 C max. (package surface temperature) Pin temperature: 300 C max., Time: 3 seconds max. (per side of device) Symbol IR35-00-2 VP15-00-2 WS66-00-1 --
Caution Do not use two or more soldering methods in combination (except the partial heating method). (2) PD17230MC-xxx-5A4: PD17231MC-xxx-5A4: PD17232MC-xxx-5A4: PD17233MC-xxx-5A4: PD17234MC-xxx-5A4: PD17235MC-xxx-5A4: PD17236MC-xxx-5A4:
Soldering Method Infrated Reflow VPS Wave soldering Partial heating
30-pin 30-pin 30-pin 30-pin 30-pin 30-pin 30-pin
plastic plastic plastic plastic plastic plastic plastic
shrink shrink shrink shrink shrink shrink shrink
SOP SOP SOP SOP SOP SOP SOP
(300 (300 (300 (300 (300 (300 (300
mil) mil) mil) mil) mil) mil) mil)
Symbol IR35-00-3 VP15-00-3 WS66-00-1 --
Soldering Conditions Package peak temperature: 235 C, Time: 30 seconds max. (210 C min.), Number of times: 3 max. Package peak temperature: 215 C, Time: 40 seconds max. (200 C min.), Number of times: 3 max. Solder bath temperature: 260 C max, Time: 10 seconds max., Number of times: once, preheating temperature: 120 C max. (package surface temperature) Pin temperature: 300 C max., Time: 3 seconds max. (per side of device)
Caution Do not use two or more soldering methods in combination (except the partial heating method).
84
Data Sheet U14360EJ1V0DS00
PD17230, 17231, 17232, 17233, 17234, 17235, 17236
APPENDIX A. DIFFERENCES BETWEEN PD17236 AND PD17P236
PD17P236 is equipped with PROM to which data can be written by the user instead of the internal mask ROM
(program memory) of the PD17236. Table A-1 shows the differences between the PD17236 and PD17P236. The CPU functions and internal hardware of the PD17P236, 17230, 17231, 17232, 17233, 17234, 17235, and 17236 are identical. Therefore, the PD17P236 can be used to evaluate the program developed for the PD17231, 17232, 17233, 17234, 17235, and 17236 system. Note, however, that some of the electrical specifications such as supply current and low-voltage detection voltage of the PD17P236 are different from those of the
PD17231, 17232, 17233, 17234, 17235, and 17236.
Table A-1. Differences among PD17236 and PD17P236
Product Name Item Program memory
PD17P236 PD17P236M1, 17P236M2, 17P236M3, 17P236M4
One-time PROM 32K bytes (16384 x 16) (0000H-3FFFH) Mask ROM
PD17236
Data memory Input/output of P1A0 pin
223 x 4 bits * Input (PD17P236M2, 17P236M4) * Output (PD17P236M1, 17P236M3) * RfX = fX/2 (PD17P236M1, 17P236M2) * RfX = fX (PD17P236M3, 17P236M4) Provided Provided * 2 s (VDD = 3.0 to 3.6 V) * 4 s (VDD = 2.2 to 3.6 V) VDD = 2.2 to 3.6 V * 28-pin plastic SOP (375 mil) * 30-pin plastic shrink SOP (300 mil) Any (mask option)
Clock selection for carrier generation
Any (mask option)
Low-voltage detection circuit VPP pin, operation mode select pin Instruction execution time
Any (mask option) Not provided * 2 s (VDD = 2.2 to 3.6 V) * 4 s (VDD = 2.0 to 3.6 V) VDD = 2.0 to 3.6 V
Supply voltage Packag
Note
Although the circuit configuration is identical, its electrical characteristics differ depending on the product.
Data Sheet U14360EJ1V0DS00
85
PD17230, 17231, 17232, 17233, 17234, 17235, 17236
APPENDIX B. FUNCTIONAL COMPARISON OF PD17236 SUBSERIES RELATED PRODUCTS
Product Name PD17201A PD17207 PD17202A PD17215 Item ROM capacity (bit) RAM capacity (bit) LCD controller/driver 3072 x 16 4096 x 16 2048 x 16 112 x 4 96 segments max. 4096 x 16 111 x 4 Not provided 6144 x 16 8192 x 16
PD17216
PD17217
PD17218
336 x 4 136 segments max.
223 x 4
Infrared remote controller carrier generator (REM) I/O ports External interrupt (INT)
LED output is high-active LED output is low-active 19 lines 1 line (rising-edge detection) 4 channels (8-bit A/D) 2 channels

Provided (without LED output)
16 lines
20 lines 1 line (rising-edge, falling-edge detection)
Analog input Timer
Not provided 2 channels

8-bit timer Watch timer
8-bit timer Basic interval timer
Watchdog timer Low-voltage detector Serial interface Stack Instruction execution time Main system clock circuitNote Not provided 1 channel
Provided (WDOUT output) Provided (WDOUT output) Not provided 5 levels (3 levels for multiplexed interrupt) 4 s (4 MHz: with ceramic or crystal resonator, VDD = 2.2 to 5.5 V) * 2 s (8 MHz ceramic resonator: in high-speed mode, VDD = 3.5 to 5.5 V) * 4 s (4 MHz ceramic resonator: in high-speed mode, VDD = 2.2 to 5.5 V) * 8 s (2 MHz ceramic resonator: in high-speed mode, VDD = 2.0 to 5.5 V) Not provided
Subsystem clock Supply voltage (With subsystem clock) Standby function Package
488 s (32.768 kHz: with crystal resonator, VDD = 2.0 to 5.5 V) VDD = 2.2 to 5.5 V (VDD = 2.0 to 5.5 V)
VDD = 2.0 to 5.5 V
STOP, HALT 80-pin plastic QFP 64-pin plastic QFP 28-pin plastic SOP 28-pin plastic shrink DIP
One-time PROM products
PD17P207
PD17P202A
PD17P218
Note
Note that although all the products have the same circuit construction, the electrical specifications differ dependant on each product.
86
Data Sheet U14360EJ1V0DS00
PD17230, 17231, 17232, 17233, 17234, 17235, 17236
PD17225 PD17226 PD17227 PD17228 PD17230 PD17231 PD17232 PD17233 PD17234 PD17235 PD17236
2048 x 16 4096 x 16 6144 x 16 8192 x 16 2048 x 16 4096 x 16 6144 x 16 8192 x 16 10240 x 16 12288 x 16 16384 x 16 111 x 4 Not provided 223 x 4
Provided (without LED output)
20 pins
21 pins 1 pin (rising edge, falling edge detection)
Not provided 2 channels

8-bit timer Basic interval timer Provided Provided
Provided (WDOUT output) Provided (WDOUT output) Not provided 5 levels (3 nesting levels)
* 2 s (8-MHz ceramic resonator: in high-speed mode, VDD = 2.2 to 3.6 V) * 4 s (4-MHz ceramic resonator: in high-speed mode, VDD = 2.0 to 3.6 V)
Not provided
VDD = 2.0 to 3.6 V
STOP, HALT 28-pin plastic SOP 28-pin plastic shrink DIP 30-pin plastic shrink SOP 30-pin plastic shrink SOP 28-pin plastic shrink SOP 30-pin plastic shrink SOP
PD17P228
PD17P236
Data Sheet U14360EJ1V0DS00
87
PD17230, 17231, 17232, 17233, 17234, 17235, 17236
APPENDIX C. DEVELOPMENT TOOLS
To develop the programs for the PD17235 subseries, the following development tools are available: Hardware
Name In-circuit emulator IE-17K, IE-17K-ETNote 1 Remarks IE-17K and IE-17K-ET are the in-circuit emulators used in common with the 17K series microcontroller. IE-17K and IE-17K-ET are connected to a PC-9800 series or IBM PC/ATTM compatible machines as the host machine with RS-232C. By using these in-circuit emulators with a system evaluation board corresponding to the microcomputer, the emulators can emulate the microcomputer. A higher level debugging environment can be provided by using man-machine interface SIMPLEHOST TM. This is an SE board for PD17236 subseries. It can be used alone to evaluate a system or in combination with an in-circuit emulator for debugging. EP-17K28GT is an emulation probe for 17K series 28-pin SOP (GM-3756). When used with EV-9500GT-28Note 2, it connects an SE board to the target system. EP-17K30GS is an emulation probe for 17K series 30-pin shrink SOP (MC-5A4). When used with EV-9500GT-30Note 3, it connects an SE board to the target system. EV-9500GT-28 is a conversion adapter for 28-pin SOP (375 mil) and is used to connect EP-17K28GT to the target system. The EV-9500GT-30 is a conversion adapter for the 30-pin shrink SOP (300 mil). It is used to connect the EP-17K30GS and target system. AF-9706, AF-9708, and AF-9709 are PROM programmers corresponding to PD17P236. By connecting program adapter PA-17P236 to this PROM programmer, PD17P236 can be programmed. PA-17P236 are adapters that is used to program PD17P236, and is used in combination with AF-9706, AF-9708, or AF-9709.
SE board (SE-17235) Emulation probe (EP-17K28GT) Emulation probe (EP-17K30GS) Conversion adapter (EV-9500GT-28Note 2) Conversion adapter (EV-9500GT-30Note 3) PROM programmer (AF-9706Note 4, AF-9708Note 4, AF-9709Note 4) Program adapter (PA-17P236)
Notes 1. Low-cost model: External power supply type 2. Two EV-9500GT-28s are supplied with the EP-17K28GT. Five EV-9500GT-28s are optionally available as a set. 3. Two EV-9500GT-30 are supplied with the EP-17K30GS. Five EV-9500GT-30s are optionally available as a set. 4. These are products from Ando Electric Co., Ltd. For details, consult Ando Electric Co., Ltd. (Tel: 03-37331166).
88
Data Sheet U14360EJ1V0DS00
PD17230, 17231, 17232, 17233, 17234, 17235, 17236
Software
Name 17K assembler (RA17K) Outline The RA17K is an assembler common to the 17K series products. When developing the program of devices, RA17K is used in combination with a device file (AS17225). Host Machine PC-9800 series IBM PC/AT compatible machine OS Japanese Windows
TM
Supply 3.5" 2HD
Order Code
SAA13RA17K SAB13RA17K SBB13RA17K
Japanese Windows
3.5" 2HC
English Windows
17K series C-like compiler (emlC-17KTM)
The emlC-17K is a C-like compiler common to the 17K series. Used in combination with the RA17K.
PC-9800 series IBM PC/AT compatible machine
Japanese Windows
3.5" 2HD
SAA13CC17K SAB13CC17K SBB13CC17K
Japanese Windows
3.5" 2HC
English Windows
Device file (AS17235)
The AS17235 is a device file for PD17230, 17231, 17232, 17233, 17234, 17235, and 17236 respectively, and are used in combination with an assembler for the 17K series (RA17K).
PC-9800 series IBM PC/AT compatible machine
Japanese Windows
3.5" 2HD
SAA13AS17235 SAB13AS17235 SBB13AS17235
Japanese Windows
3.5" 2HC
English Windows
Support software (SIMPLEHOST)
SIMPLEHOST is a software package that enables man-machine interface on the Windows when a program is developed by using an incircuit emulator and a personal computer.
PC-9800 series IBM PC/AT compatible machine
Japanese Windows
3.5" 2HD
SAA13ID17K SAB13ID17K SBB13ID17K
Japanese Windows
3.5" 2HC
English Windows
Data Sheet U14360EJ1V0DS00
89
PD17230, 17231, 17232, 17233, 17234, 17235, 17236
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
90
Data Sheet U14360EJ1V0DS00
PD17230, 17231, 17232, 17233, 17234, 17235, 17236
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: * Device availability * Ordering information * Product release schedule * Availability of related technical literature * Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) * Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country.
NEC Electronics Inc. (U.S.)
Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288
NEC Electronics (Germany) GmbH
Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580
NEC Electronics Hong Kong Ltd.
Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044
NEC Electronics Hong Kong Ltd. NEC Electronics (France) S.A.
Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411
NEC Electronics (Germany) GmbH
Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490
NEC Electronics (France) S.A. NEC Electronics (UK) Ltd.
Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 Spain Office Madrid, Spain Tel: 91-504-2787 Fax: 91-504-2860
NEC Electronics Singapore Pte. Ltd.
United Square, Singapore 1130 Tel: 65-253-8311 Fax: 65-250-3583
NEC Electronics Taiwan Ltd. NEC Electronics Italiana s.r.l.
Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99
NEC Electronics (Germany) GmbH
Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388
Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951
NEC do Brasil S.A.
Electron Devices Division Rodovia Presidente Dutra, Km 214 07210-902-Guarulhos-SP Brasil Tel: 55-11-6465-6810 Fax: 55-11-6465-6829
J99.1
Data Sheet U14360EJ1V0DS00
91
PD17230, 17231, 17232, 17233, 17234, 17235, 17236
emlC-17K and SIMPLEHOST are trademarks of NEC Corporation.
Windows is either a registered trademark or a trademark of Microsoft Corporation in the United States and/or other countries. PC/AT is a trademark of IBM Corporation.
The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative.
* The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. * No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. * NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. * Descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. * While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. * NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance.
M7 98.8


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